Inventor · disambiguated record
Pratik A. Patel
Also filed as: PATEL PRATIK · PATEL PRATIK A
18 granted patents·16 pending applications·90 citations·filing 2009–2025
90Inventor score
Top patents by PatentIndex Score
34 records- 0196US8384122B1Tunneling transistor suitable for low voltage operationUNIV CALIFORNIA·Filed 2009·Granted Feb 26, 2013·78 cites·18 claims
- 0286US11183592B2Field effect transistor with a hybrid gate spacer including a low-k dielectric materialINTEL CORP·Filed 2016·Granted Nov 23, 2021·4 cites·17 claims
- 0385US12027417B2Source or drain structures with high germanium concentration capping layerINTEL CORP·Filed 2020·Granted Jul 2, 2024·2 cites·16 claims
- 0484US12224326B2Contact architecture for capacitance reduction and satisfactory contact resistanceINTEL CORP·Filed 2023·Granted Feb 11, 2025·0 cites·24 claims
- 0577US11824097B2Contact architecture for capacitance reduction and satisfactory contact resistanceINTEL CORP·Filed 2022·Granted Nov 21, 2023·0 cites·20 claims
- 0676US2025151363A1Contact architecture for capacitance reduction and satisfactory contact resistanceINTEL CORP·Filed 2025·Application pending·0 cites
- 0776US2023253499A1Diffused tip extension transistorINTEL CORP·Filed 2023·Application pending·0 cites
- 0873US11101268B2Transistors employing non-selective deposition of source/drain materialINTEL CORP·Filed 2017·Granted Aug 24, 2021·2 cites·18 claims
- 0972US11282930B2Contact architecture for capacitance reduction and satisfactory contact resistanceINTEL CORP·Filed 2020·Granted Mar 22, 2022·0 cites·20 claims
- 1071US11152461B2Semiconductor layer between source/drain regions and gate spacersINTEL CORP·Filed 2018·Granted Oct 19, 2021·1 cites·20 claims
- 1171US9117893B1Tunneling transistor suitable for low voltage operationHU CHENMING·Filed 2013·Granted Aug 25, 2015·3 cites·19 claims
- 1270US11664452B2Diffused tip extension transistorINTEL CORP·Filed 2020·Granted May 30, 2023·0 cites·20 claims
- 1368US12426299B2Fin shaping and integrated circuit structures resulting therefromINTEL CORP·Filed 2022·Granted Sep 23, 2025·0 cites·11 claims
- 1467US12469780B2Integrated circuit structure with recessed self-aligned deep boundary viaINTEL CORP·Filed 2022·Granted Nov 11, 2025·0 cites·20 claims
- 1567US11908940B2Field effect transistor with a hybrid gate spacer including a low-k dielectric materialINTEL CORP·Filed 2021·Granted Feb 20, 2024·0 cites·20 claims
- 1663US10872977B2Diffused tip extension transistorINTEL CORP·Filed 2019·Granted Dec 22, 2020·0 cites·20 claims
- 1763US2023197855A1Gate-all-around integrated circuit structures having source or drain structures with regrown central portionsHASAN MOHAMMAD·Filed 2021·Application pending·0 cites
- 1861US11901457B2Fin shaping and integrated circuit structures resulting therefromINTEL CORP·Filed 2019·Granted Feb 13, 2024·0 cites·23 claims
- 1958US10872960B2Contact architecture for capacitance reduction and satisfactory contact resistanceINTEL CORP·Filed 2016·Granted Dec 22, 2020·0 cites·25 claims
- 2056US12507449B2Gate-all-around integrated circuit structures having necked featureINTEL CORP·Filed 2022·Granted Dec 23, 2025·0 cites·20 claims
- 2156US10304956B2Diffused tip extension transistorINTEL CORP·Filed 2013·Granted May 28, 2019·0 cites·24 claims
- 2250US2023197838A1Gate-all-around integrated circuit structures having source or drain-last structuresHASAN MOHAMMAD·Filed 2021·Application pending·0 cites
- 2350US2023320057A1Recessed transistor terminal via jumpersINTEL CORP·Filed 2022·Application pending·0 cites
- 2449US2023084182A1Selective depopulation of gate-all-around semiconductor devicesINTEL CORP·Filed 2021·Application pending·0 cites
- 2549US2023420512A1Integrated circuit structure with backside power stapleINTEL CORP·Filed 2022·Application pending·0 cites
- 2649US2024404917A1Self-aligned via patterning for backside interconnectsINTEL CORP·Filed 2023·Application pending·0 cites
- 2748US2023079586A1Selectively thinned gate-all-around (gaa) structuresINTEL CORP·Filed 2021·Application pending·0 cites
- 2848US2023197714A1Gate-all-around integrated circuit structures having backside contact self-aligned to epitaxial sourceINTEL CORP·Filed 2021·Application pending·0 cites
- 2948US2023095191A1Transistors with reduced epitaxial source/drain span via etch-back for improved cell scalingINTEL CORP·Filed 2021·Application pending·0 cites
- 3047US2023207560A1Transistors with doped intrinsic germanium caps on source drain regions for improved contact resistanceINTEL CORP·Filed 2021·Application pending·0 cites
- 3145US2023207696A1Integrated circuits with gate plugs to induce compressive channel strainHASAN MOHAMMAD·Filed 2021·Application pending·0 cites
- 3244US2023207651A1Gate-all-around integrated circuit structures having source or drain structures with substrate connection portionsHASAN MOHAMMAD·Filed 2021·Application pending·0 cites
- 3344US2021408275A1Source or drain structures with high surface germanium concentrationINTEL CORP·Filed 2020·Application pending·0 cites
- 3434US2020161440A1Metal to source/drain contact area using thin nucleation layer and sacrificial epitaxial filmINTEL CORP·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →