Inventor · disambiguated record
Jerome J. Johnson
Also filed as: JOHNSON JEROME J
30 granted patents·1,922 citations·filing 1997–2017
98Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO15COMPAQ COMPUTER CORP10CADENCE DESIGN SYSTEMS INC3COMPAQ INFORMATION TECHNOLOGIE2
Top patents by PatentIndex Score
30 records- 0197US7010652B2Method for supporting multi-level striping of non-homogeneous memory to maximize concurrencyHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Mar 7, 2006·136 cites·12 claims
- 0297US6785785B2Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrencyHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 31, 2004·140 cites·16 claims
- 0397US6684292B2Memory module resyncHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jan 27, 2004·148 cites·11 claims
- 0496US7194577B2Memory latency and bandwidth optimizationsHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 20, 2007·128 cites·17 claims
- 0596US6938133B2Memory latency and bandwidth optimizationsHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 30, 2005·144 cites·19 claims
- 0695US6766469B2Hot-replace of memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jul 20, 2004·139 cites·63 claims
- 0794US7320086B2Error indication in a raid memory systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Jan 15, 2008·41 cites·18 claims
- 0894US6286083B1Computer system with adaptive memory arbitration schemeCOMPAQ COMPUTER CORP·Filed 1998·Granted Sep 4, 2001·213 cites·26 claims
- 0993US10275306B1System and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurationsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Apr 30, 2019·14 cites·20 claims
- 1093US6832340B2Real-time hardware memory scrubbingHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Dec 14, 2004·90 cites·40 claims
- 1191US6854070B2Hot-upgrade/hot-add memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Feb 8, 2005·75 cites·56 claims
- 1290US6785835B2Raid memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 31, 2004·47 cites·36 claims
- 1388US10719058B1System and method for memory control having selectively distributed power-on processingCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jul 21, 2020·11 cites·15 claims
- 1484US10956342B1Variable channel multi-controller memory systemCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Mar 23, 2021·5 cites·19 claims
- 1584US7028213B2Error indication in a raid memory systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Apr 11, 2006·36 cites·33 claims
- 1684US6356972B1System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefromCOMPAQ INFORMATION TECHNOLOGIE·Filed 2001·Granted Mar 12, 2002·34 cites·17 claims
- 1783US6505260B2Computer system with adaptive memory arbitration schemeCOMPAQ INFORMATION TECHNOLOGIE·Filed 2001·Granted Jan 7, 2003·34 cites·54 claims
- 1879US6640282B2Hot replace power control sequence logicHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Oct 28, 2003·25 cites·23 claims
- 1976US6160562ASystem and method for aligning an initial cache line of data read from local memory by an input/output deviceCOMPAQ COMPUTER CORP·Filed 1998·Granted Dec 12, 2000·73 cites·18 claims
- 2074US6202101B1System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefromCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 13, 2001·58 cites·10 claims
- 2173US6247102B1Computer system employing memory controller and bridge interface permitting concurrent operationCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 12, 2001·68 cites·41 claims
- 2272US6832286B2Memory auto-prechargeHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Dec 14, 2004·17 cites·28 claims
- 2372US6272651B1System and method for improving processor read latency in a system employing error checking and correctionCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 7, 2001·61 cites·19 claims
- 2472US5949436AAccelerated graphics port multiple entry gart cache allocation system and methodCOMPAQ COMPUTER CORP·Filed 1997·Granted Sep 7, 1999·67 cites·24 claims
- 2571US6892271B2Memory module resyncHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted May 10, 2005·13 cites·46 claims
- 2670US6981095B1Hot replace power control sequence logicHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Dec 27, 2005·12 cites·32 claims
- 2764US6279065B1Computer system with improved memory accessCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 21, 2001·43 cites·18 claims
- 2851US6209052B1System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiterCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 27, 2001·23 cites·18 claims
- 2943US6199118B1System and method for aligning an initial cache line of data read from an input/output device by a central processing unitCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 6, 2001·15 cites·18 claims
- 3040US6216190B1System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral busCOMPAQ COMPUTER CORP·Filed 1998·Granted Apr 10, 2001·12 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →