Inventor · disambiguated record
Jeremy Rutledge Levitt
Also filed as: LEVITT JEREMY · LEVITT JEREMY R · LEVITT JEREMY RUTLEDGE
10 granted patents·1 pending application·169 citations·filing 2001–2016
90Inventor score
Technology areasG06F
Files withMENTOR GRAPHICS CORP4SEAWRIGHT JAMES ANDREW GARRARD3LEVITT JEREMY RUTLEDGE2LEVITT JEREMY R1
Top patents by PatentIndex Score
11 records- 0193US6848088B1Measure of analysis performed in property checkingMENTOR GRAPHICS CORP·Filed 2002·Granted Jan 25, 2005·69 cites·10 claims
- 0286US7890897B2Measure of analysis performed in property checkingMENTOR GRAPHICS CORP·Filed 2007·Granted Feb 15, 2011·11 cites·23 claims
- 0385US8418121B2Measure of analysis performed in property checkingLEVITT JEREMY RUTLEDGE·Filed 2011·Granted Apr 9, 2013·7 cites·21 claims
- 0485US7454324B1Selection of initial states for formal verificationSEAWRIGHT JAMES ANDREW GARRARD·Filed 2003·Granted Nov 18, 2008·57 cites·18 claims
- 0575US7318205B2Measure of analysis performed in property checkingLEVITT JEREMY RUTLEDGE·Filed 2004·Granted Jan 8, 2008·15 cites·26 claims
- 0670US7487483B2Clock model for formal verification of a digital circuit descriptionSEAWRIGHT JAMES ANDREW GARRARD·Filed 2006·Granted Feb 3, 2009·5 cites·6 claims
- 0768US9262557B2Measure of analysis performed in property checkingMENTOR GRAPHICS CORP·Filed 2013·Granted Feb 16, 2016·1 cites·5 claims
- 0857US9684760B2Measure of analysis performed in property checkingMENTOR GRAPHICS CORP·Filed 2016·Granted Jun 20, 2017·0 cites·18 claims
- 0957US8060847B2Clock model for formal verification of a digital circuit descriptionSEAWRIGHT JAMES ANDREW GARRARD·Filed 2008·Granted Nov 15, 2011·1 cites·11 claims
- 1037US2007299648A1Reuse of learned information to simplify functional verification of a digital circuitLEVITT JEREMY R·Filed 2003·Application pending·0 cites
- 1127USD477476SFurniture leg footFiled 2001·Granted Jul 22, 2003·3 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →