Inventor · disambiguated record
Jerome Lopez
Also filed as: LOPEZ JEROME · LOPEZ JÉRÔME
15 granted patents·12 pending applications·19 citations·filing 2004–2025
88Inventor score
Files withST MICROELECTRONICS GRENOBLE 215ST MICROELECTRONICS INT NV3ST MICROELECTRONICS SA2LOPEZ JEROME1MAUNA KEA TECHNOLOGIES1
Top patents by PatentIndex Score
27 records- 0184US2025070081A1Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic deviceST MICROELECTRONICS GRENOBLE 2·Filed 2024·Application pending·0 cites
- 0279US7838417B2Semiconductor package with a chip on a support plateST MICROELECTRONICS SA·Filed 2009·Granted Nov 23, 2010·8 cites·17 claims
- 0377US12170262B2Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic deviceST MICROELECTRONICS GRENOBLE 2·Filed 2022·Granted Dec 17, 2024·0 cites·10 claims
- 0476US12218287B2Electronic packageST MICROELECTRONICS GRENOBLE 2·Filed 2023·Granted Feb 4, 2025·0 cites·20 claims
- 0576US10600704B2Electronic device comprising a support substrate and an encapsulating cover for an electronic componentST MICROELECTRONICS GRENOBLE 2·Filed 2018·Granted Mar 24, 2020·2 cites·11 claims
- 0674US12249549B2Package for an integrated circuit and manufacturing methodST MICROELECTRONICS GRENOBLE 2·Filed 2024·Granted Mar 11, 2025·0 cites·12 claims
- 0767US11862757B2Electronic packageST MICROELECTRONICS GRENOBLE 2·Filed 2021·Granted Jan 2, 2024·0 cites·19 claims
- 0866US11557566B2Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic deviceST MICROELECTRONICS GRENOBLE 2·Filed 2020·Granted Jan 17, 2023·0 cites·14 claims
- 0963US11984373B2Package for integrated circuit and manufacturing methodST MICROELECTRONICS GRENOBLE 2·Filed 2021·Granted May 14, 2024·0 cites·13 claims
- 1062US2025079259A1Package for integrated circuit with heat dissipationST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1161US10643970B2Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic deviceST MICROELECTRONICS GRENOBLE 2·Filed 2019·Granted May 5, 2020·0 cites·5 claims
- 1258US2024087977A1Integrated circuit package heat sinkST MICROELECTRONICS GRENOBLE 2·Filed 2023·Application pending·0 cites
- 1356US2023411271A1Integrated circuit packagesST MICROELECTRONICS GRENOBLE 2·Filed 2023·Application pending·0 cites
- 1454US10892201B2Electronic device comprising a support substrate and an encapsulating cover for an electronic componentSTMICROELECTRONCIS GRENOBLE 2 SAS·Filed 2020·Granted Jan 12, 2021·0 cites·11 claims
- 1554US10224306B2Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic deviceST MICROELECTRONICS GRENOBLE 2·Filed 2017·Granted Mar 5, 2019·0 cites·6 claims
- 1654US2025372403A1Interconnection substrate and method of manufacturing such a substrateST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 1753US10765412B2Endoscopic instrument with support footROSA BENOIT·Filed 2012·Granted Sep 8, 2020·2 cites·13 claims
- 1852US7573141B2Semiconductor package with a chip on a support plateST MICROELECTRONICS SA·Filed 2004·Granted Aug 11, 2009·5 cites·14 claims
- 1948US8178959B2Process for fabricating a semiconductor component support, support and semiconductor deviceLOPEZ JEROME·Filed 2009·Granted May 15, 2012·2 cites·10 claims
- 2046US2023290712A1Interconnection substrate and method of manufacturing such a substrateST MICROELECTRONICS GRENOBLE 2·Filed 2023·Application pending·0 cites
- 2145US2020335466A1Centripetal bumping layout and methodST MICROELECTRONICS ALPS SAS·Filed 2020·Application pending·0 cites
- 2241US2025285927A1Method of manufacturing electronic componentsST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 2340US2022200117A1Transmission deviceST MICROELECTRONICS GRENOBLE 2·Filed 2021·Application pending·0 cites
- 2440US2011015529A1Methylene blue based fibred fluorescence microscopyMAUNA KEA TECHNOLOGIES·Filed 2007·Application pending·0 cites
- 2539US2015022987A1Electronic device comprising an integrated circuit chip provided with projecting electrical connection padsST MICROELECTRONICS CROLLES 2·Filed 2014·Application pending·0 cites
- 2635US10292259B2Electrical shielding using bar vias and associated methodsST MICROELECTRONICS GRENOBLE 2·Filed 2016·Granted May 14, 2019·0 cites·9 claims
- 2729US2012133039A1Semiconductor package with thermal via and method of fabricationPRUVOST JULIEN·Filed 2011·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Jerome Lopez files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →