Inventor · disambiguated record
Jeffrey R. Rearick
Also filed as: REARICK JEFFREY · REARICK JEFFREY R · REARICK JEFFREY RICHARD
25 granted patents·4 pending applications·446 citations·filing 1998–2024
96Inventor score
Files withAGILENT TECHNOLOGIES INC11AVAGO TECHNOLOGIES GENERAL IP10ADVANCED MICRO DEVICES INC4BRATT JOHN1HEWLETT PACKARD CO1
Top patents by PatentIndex Score
29 records- 0193US6556938B1Systems and methods for facilitating automated test equipment functionality within integrated circuitsAGILENT TECHNOLOGIES INC·Filed 2000·Granted Apr 29, 2003·55 cites·30 claims
- 0287US7352165B2Delay-locked loop and a method of testing a delay-locked loopAVAGO TECHNOLOGIES GENERAL IP·Filed 2006·Granted Apr 1, 2008·15 cites·4 claims
- 0387US6995554B2Delay-locked loop and a method of testing a delay-locked loopAGILENT TECHNOLOGIES INC·Filed 2004·Granted Feb 7, 2006·34 cites·8 claims
- 0487US6067651ATest pattern generator having improved test sequence compactionHEWLETT PACKARD CO·Filed 1998·Granted May 23, 2000·67 cites·31 claims
- 0586US6762614B2Systems and methods for facilitating driver strength testing of integrated circuitsAGILENT TECHNOLOGIES INC·Filed 2002·Granted Jul 13, 2004·31 cites·9 claims
- 0685US7143324B2System and method for automatic masking of compressed scan chains with unbalanced lengthsAVAGO TECHNOLOGIES GENERAL IP·Filed 2004·Granted Nov 28, 2006·41 cites·15 claims
- 0783US7411407B2Testing target resistances in circuit assembliesAGILENT TECHNOLOGIES INC·Filed 2006·Granted Aug 12, 2008·13 cites·19 claims
- 0881US7043674B2Systems and methods for facilitating testing of pads of integrated circuitsREARICK JEFFREY R·Filed 2003·Granted May 9, 2006·27 cites·21 claims
- 0980US7519875B2Method and apparatus for enabling a user to determine whether a defective location in a memory device has been remapped to a redundant memory portionAVAGO TECHNOLOGIES GENERAL IP·Filed 2005·Granted Apr 14, 2009·13 cites·19 claims
- 1080US7123001B2Delay-locked loop and a method of testing a delay-locked loopAVAGO TECHNOLOGIES GENERAL IP·Filed 2006·Granted Oct 17, 2006·10 cites·6 claims
- 1179US7139948B2Method for determining the impact on test coverage of scan chain parallelization by analysis of a test set for independently accessible flip-flopsAVAGO TECHNOLOGIES GENERAL IP·Filed 2003·Granted Nov 21, 2006·22 cites·18 claims
- 1279US6658613B2Systems and methods for facilitating testing of pad receivers of integrated circuitsAGILENT TECHNOLOGIES INC·Filed 2001·Granted Dec 2, 2003·23 cites·17 claims
- 1378US7516379B2Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)AVAGO TECHNOLOGIES GENERAL IP·Filed 2004·Granted Apr 7, 2009·21 cites·16 claims
- 1474US12399772B2Devices, systems, and methods for detecting and mitigating silent data corruptions via adaptive voltage-frequency scalingADVANCED MICRO DEVICES INC·Filed 2024·Granted Aug 26, 2025·0 cites·20 claims
- 1574US6859059B2Systems and methods for testing receiver terminations in integrated circuitsAGILENT TECHNOLOGIES INC·Filed 2003·Granted Feb 22, 2005·17 cites·20 claims
- 1673US7640468B2Method and apparatus for an embedded time domain reflectometry testAGILENT TECHNOLOGIES INC·Filed 2004·Granted Dec 29, 2009·17 cites·23 claims
- 1769US11966283B1Devices, systems, and methods for detecting and mitigating silent data corruptions via adaptive voltage-frequency scalingADVANCED MICRO DEVICES INC·Filed 2022·Granted Apr 23, 2024·0 cites·20 claims
- 1869US6577980B1Systems and methods for facilitating testing of pad receivers of integrated circuitsAGILENT TECHNOLOGIES INC·Filed 2000·Granted Jun 10, 2003·12 cites·28 claims
- 1962US7222278B2Programmable hysteresis for boundary-scan testingAVAGO TECHNOLOGIES GENERAL IP·Filed 2003·Granted May 22, 2007·9 cites·20 claims
- 2061US6986085B2Systems and methods for facilitating testing of pad drivers of integrated circuitsAGILENT TECHNOLOGIES INC·Filed 2002·Granted Jan 10, 2006·8 cites·20 claims
- 2159US2025096136A1Devices, systems, and methods for a programmable three-dimensional semiconductor power delivery networkADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 2254US7079973B2Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)AVAGO TECHNOLOGIES GENERAL IP·Filed 2004·Granted Jul 18, 2006·6 cites·10 claims
- 2352US2025306093A1Periodic In-Field Testing of System on Chip Functional UnitsADVANCED MICRO DEVICES INC·Filed 2024·Application pending·0 cites
- 2448US6907376B2Systems and methods for facilitating testing of pad receivers of integrated circuitsAGILENT TECHNOLOGIES INC·Filed 2003·Granted Jun 14, 2005·3 cites·12 claims
- 2545US6741946B2Systems and methods for facilitating automated test equipment functionality within integrated circuitsAGILENT TECHNOLOGIES INC·Filed 2003·Granted May 25, 2004·2 cites·30 claims
- 2641US7580806B2Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)AVAGO TECHNOLOGIES GENERAL IP·Filed 2006·Granted Aug 25, 2009·0 cites·8 claims
- 2737US2006156139A1Systems and methods for facilitating testing of integrated circuitsROHRBAUGH JOHN·Filed 2005·Application pending·0 cites
- 2837US2006150136A1Systems and methods for designing integrated circuitsBRATT JOHN·Filed 2005·Application pending·0 cites
- 2936US7502978B2Systems and methods for reconfiguring scan chainsAVAGO TECHNOLOGIES GENERAL IP·Filed 2005·Granted Mar 10, 2009·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →