Inventor · disambiguated record
Jens Rosenbusch
Also filed as: ROSENBUSCH JENS
15 granted patents·7 pending applications·33 citations·filing 1998–2025
88Inventor score
Top patents by PatentIndex Score
22 records- 0178US10056145B2Resistive memory transition monitoringINFINEON TECHNOLOGIES AG·Filed 2017·Granted Aug 21, 2018·4 cites·20 claims
- 0277US10319460B2Systems and methods utilizing a flexible read reference for a dynamic read windowINFINEON TECHNOLOGIES AG·Filed 2013·Granted Jun 11, 2019·6 cites·17 claims
- 0374US11640332B1Execute in place architecture with integrity checkINFINEON TECHNOLOGIES AG·Filed 2021·Granted May 2, 2023·1 cites·20 claims
- 0467US6465868B1Integrated circuit having capacitive elementsINFINEON TECHNOLOGIES AG·Filed 2000·Granted Oct 15, 2002·14 cites·12 claims
- 0566US12196803B2Signal testINFINEON TECHNOLOGIES AG·Filed 2022·Granted Jan 14, 2025·0 cites·20 claims
- 0658US2025258469A1Standby entity for hardware functionsINFINEON TECHNOLOGIES AG·Filed 2025·Application pending·0 cites
- 0753US11995015B2Data processing device and method for transmitting data over a busINFINEON TECHNOLOGIES AG·Filed 2022·Granted May 28, 2024·0 cites·15 claims
- 0852US9389999B2System and method for emulating an EEPROM in a non-volatile memory deviceKERN THOMAS·Filed 2012·Granted Jul 12, 2016·1 cites·22 claims
- 0950USRE39124EIntegrated circuit having capacitive elementsINFINEON TECHNOLOGIES AG·Filed 2003·Granted Jun 13, 2006·4 cites·12 claims
- 1047US10311955B2Resistive memory transition monitoringINFINEON TECHNOLOGIES AG·Filed 2018·Granted Jun 4, 2019·0 cites·19 claims
- 1146US12316346B2Error processing and correction of adjacent 2-bit errorsINFINEON TECHNOLOGIES AG·Filed 2023·Granted May 27, 2025·0 cites·17 claims
- 1246US6998874B2Method and apparatus for the transmission of differential signalsINFINEON TECHNOLOGIES AG·Filed 2002·Granted Feb 14, 2006·1 cites·3 claims
- 1344US2024380409A1Electronic deviceINFINEON TECHNOLOGIES AG·Filed 2024·Application pending·0 cites
- 1443US11619668B2Integrated circuit with self-test circuit, method for operating an integrated circuit with self-test circuit, multi-core processor device and method for operating a multi-core processor deviceINFINEON TECHNOLOGIES AG·Filed 2021·Granted Apr 4, 2023·0 cites·24 claims
- 1542US2014198583A1Method and System for Reducing the Size of Nonvolatile MemoriesINFINEON TECHNOLOGIES AG·Filed 2013·Application pending·0 cites
- 1640US9343179B2Word line address scanINFINEON TECHNOLOGIES AG·Filed 2013·Granted May 17, 2016·0 cites·20 claims
- 1739US2015179270A1Method and System for Reducing the Size of Nonvolatile MemoriesINFINEON TECHNOLOGIES AG·Filed 2015·Application pending·0 cites
- 1836US9569354B2System and method to emulate an electrically erasable programmable read-only memoryINFINEON TECHNOLOGIES AG·Filed 2013·Granted Feb 14, 2017·0 cites·18 claims
- 1936US2015169438A1Method and device for incrementing an erase counterINFINEON TECHNOLOGIES AG·Filed 2013·Application pending·0 cites
- 2035US2014241055A1Method and System for Reducing the Complexity of Electronically Programmable Nonvolatile MemoryINFINEON TECHNOLOGIES AG·Filed 2013·Application pending·0 cites
- 2126US6351147B1Configuration and method for matching output drivers of integrated circuits to specified conditionsINFINEON TECHNOLOGIES AG·Filed 1998·Granted Feb 26, 2002·2 cites·5 claims
- 2226US2014075093A1Method and system for implicit or explicit online repair of memoryWIESNER ROBERT·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →