Inventor · disambiguated record
Jeffrey Smith
Also filed as: SMITH JEFFREY · SMITH JEFFREY A · SMITH JEFFREY T · SMITH JEFFREY THOMAS
109 granted patents·22 pending applications·1,186 citations·filing 1984–2025
99Inventor score
Files withTOKYO ELECTRON LTD115QUALCOMM INC4APPLIED MICRO CIRCUITS CORP3MICROSOFT CORP2SMITH JEFFREY T2
Top patents by PatentIndex Score
131 records- 0198US10991626B2Method for controlling transistor delay of nanowire or nanosheet transistor devicesTOKYO ELECTRON LTD·Filed 2020·Granted Apr 27, 2021·6 cites·13 claims
- 0298US10734224B2Method and device for incorporating single diffusion break into nanochannel structures of FET devicesTOKYO ELECTRON LTD·Filed 2018·Granted Aug 4, 2020·20 cites·15 claims
- 0398US10586765B2Buried power railsTOKYO ELECTRON LTD·Filed 2018·Granted Mar 10, 2020·62 cites·20 claims
- 0498US10453850B2Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabricationTOKYO ELECTRON LTD·Filed 2017·Granted Oct 22, 2019·23 cites·18 claims
- 0598US10388519B2Method and device for incorporating single diffusion break into nanochannel structures of FET devicesTOKYO ELECTRON LTD·Filed 2018·Granted Aug 20, 2019·23 cites·20 claims
- 0698US9837314B2Self-alignment of metal and via using selective depositionTOKYO ELECTRON LTD·Filed 2017·Granted Dec 5, 2017·27 cites·10 claims
- 0798US7336139B2Flexible interconnect cable with grounded coplanar waveguideAPPLIED MICRO CIRCUITS CORP·Filed 2006·Granted Feb 26, 2008·108 cites·20 claims
- 0897US11631671B23D complementary metal oxide semiconductor (CMOS) device and method of forming the sameTOKYO ELECTRON LTD·Filed 2020·Granted Apr 18, 2023·5 cites·23 claims
- 0997US11532708B2Stacked three-dimensional field-effect transistorsTOKYO ELECTRON LTD·Filed 2021·Granted Dec 20, 2022·5 cites·12 claims
- 1097US11264274B2Reverse contact and silicide process for three-dimensional logic devicesTOKYO ELECTRON LTD·Filed 2020·Granted Mar 1, 2022·5 cites·20 claims
- 1197US10833078B2Semiconductor apparatus having stacked gates and method of manufacture thereofTOKYO ELECTRON LTD·Filed 2018·Granted Nov 10, 2020·34 cites·20 claims
- 1297US10573655B2Three-dimensional semiconductor device and method of fabricationTOKYO ELECTRON LTD·Filed 2018·Granted Feb 25, 2020·14 cites·12 claims
- 1397US9997598B2Three-dimensional semiconductor device and method of fabricationTOKYO ELECTRON LTD·Filed 2017·Granted Jun 12, 2018·26 cites·20 claims
- 1497US7145411B1Flexible differential interconnect cable with isolated high frequency electrical transmission lineAPPLIED MICRO CIRCUITS CORP·Filed 2004·Granted Dec 5, 2006·146 cites·19 claims
- 1597US6797891B1Flexible interconnect cable with high frequency electrical transmission lineAPPLIED MICRO CIRCUITS CORP·Filed 2002·Granted Sep 28, 2004·211 cites·20 claims
- 1696US11545497B2CFET SRAM bit cell with three stacked device decksTOKYO ELECTRON LTD·Filed 2020·Granted Jan 3, 2023·3 cites·18 claims
- 1796US10916472B2Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using sameTOKYO ELECTRON LTD·Filed 2019·Granted Feb 9, 2021·14 cites·17 claims
- 1896US10770479B2Three-dimensional device and method of forming the sameTOKYO ELECTRON LTD·Filed 2019·Granted Sep 8, 2020·20 cites·20 claims
- 1996US10685887B2Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) deviceTOKYO ELECTRON LTD·Filed 2018·Granted Jun 16, 2020·26 cites·19 claims
- 2096US10529830B2Extension region for a semiconductor deviceTOKYO ELECTRON LTD·Filed 2017·Granted Jan 7, 2020·16 cites·14 claims
- 2196US8044746B2Flexible interconnect cable with first and second signal traces disposed between first and second ground traces so as to provide different line width and line spacing configurationsQUALCOMM INC·Filed 2010·Granted Oct 25, 2011·25 cites·14 claims
- 2295US11101173B2Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using sameTOKYO ELECTRON LTD·Filed 2019·Granted Aug 24, 2021·11 cites·27 claims
- 2395US10964706B2Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabricationTOKYO ELECTRON LTD·Filed 2019·Granted Mar 30, 2021·9 cites·10 claims
- 2495US10714391B2Method for controlling transistor delay of nanowire or nanosheet transistor devicesTOKYO ELECTRON LTD·Filed 2018·Granted Jul 14, 2020·11 cites·16 claims
- 2593US12237333B2Power wall integration for multiple stacked devicesTOKYO ELECTRON LTD·Filed 2021·Granted Feb 25, 2025·2 cites·6 claims
- 2692US11923364B2Double cross-couple for two-row flip-flop using CFETTOKYO ELECTRON LTD·Filed 2021·Granted Mar 5, 2024·2 cites·20 claims
- 2792US11665878B2CFET SRAM bit cell with two stacked device decksTOKYO ELECTRON LTD·Filed 2021·Granted May 30, 2023·2 cites·20 claims
- 2892US11114381B2Power distribution network for 3D logic and memoryTOKYO ELECTRON LTD·Filed 2019·Granted Sep 7, 2021·7 cites·20 claims
- 2992US10930764B2Extension region for a semiconductor deviceTOKYO ELECTRON LTD·Filed 2019·Granted Feb 23, 2021·6 cites·20 claims
- 3091US11488947B2Highly regular logic design for efficient 3D integrationTOKYO ELECTRON LTD·Filed 2020·Granted Nov 1, 2022·2 cites·17 claims
- 3191US7719378B2Flexible interconnect cable for an electronic assemblyQUALCOMM INC·Filed 2008·Granted May 18, 2010·19 cites·27 claims
- 3290US9721793B2Method of patterning without dummy gatesTOKYO ELECTRON LTD·Filed 2016·Granted Aug 1, 2017·6 cites·14 claims
- 3389US12336274B2Self-aligned method for vertical recess for 3D device integrationTOKYO ELECTRON LTD·Filed 2022·Granted Jun 17, 2025·1 cites·20 claims
- 3489US11264289B2Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacksTOKYO ELECTRON LTD·Filed 2020·Granted Mar 1, 2022·2 cites·19 claims
- 3588US11574845B2Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devicesTOKYO ELECTRON LTD·Filed 2020·Granted Feb 7, 2023·2 cites·13 claims
- 3688US11177250B2Method for fabrication of high density logic and memory for advanced circuit architectureTOKYO ELECTRON LTD·Filed 2020·Granted Nov 16, 2021·2 cites·20 claims
- 3788US4675820AInertial reference systemSUNDSTRAND DATA CONTROL·Filed 1984·Granted Jun 23, 1987·62 cites·8 claims
- 3887US11616053B2Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic deviceTOKYO ELECTRON LTD·Filed 2019·Granted Mar 28, 2023·4 cites·20 claims
- 3987US10847424B2Method for forming a nanowire deviceTOKYO ELECTRON LTD·Filed 2019·Granted Nov 24, 2020·4 cites·20 claims
- 4086US11764113B2Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholdsTOKYO ELECTRON LTD·Filed 2021·Granted Sep 19, 2023·1 cites·20 claims
- 4185US11646318B2Connections from buried interconnects to device terminals in multiple stacked devices structuresTOKYO ELECTRON LTD·Filed 2021·Granted May 9, 2023·1 cites·7 claims
- 4285US8379403B2Spacer-connector and circuit board assemblyQUALCOMM INC·Filed 2010·Granted Feb 19, 2013·14 cites·19 claims
- 4384US11581242B2Integrated high efficiency gate on gate coolingTOKYO ELECTRON LTD·Filed 2021·Granted Feb 14, 2023·1 cites·14 claims
- 4484US11444082B2Semiconductor apparatus having stacked gates and method of manufacture thereofTOKYO ELECTRON LTD·Filed 2020·Granted Sep 13, 2022·1 cites·20 claims
- 4583US11031287B2Fully self-aligned via with selective bilayer dielectric regrowthTOKYO ELECTRON LTD·Filed 2019·Granted Jun 8, 2021·3 cites·11 claims
- 4681US9595441B2Patterning a substrate using grafting polymer materialTOKYO ELECTRON LTD·Filed 2015·Granted Mar 14, 2017·3 cites·18 claims
- 4780US11735525B2Power delivery network for CFET with buried power railsTOKYO ELECTRON LTD·Filed 2019·Granted Aug 22, 2023·2 cites·13 claims
- 4880US9711419B2Substrate backside texturingTOKYO ELECTRON LTD·Filed 2015·Granted Jul 18, 2017·3 cites·16 claims
- 4979US11322401B2Reverse contact and silicide process for three-dimensional semiconductor devicesTOKYO ELECTRON LTD·Filed 2020·Granted May 3, 2022·1 cites·20 claims
- 5079US11201148B2Architecture for monolithic 3D integration of semiconductor devicesTOKYO ELECTRON LTD·Filed 2019·Granted Dec 14, 2021·2 cites·18 claims
Showing the top 50 of 131 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →