Inventor · disambiguated record
Jeh-Fu Tuan
Also filed as: TUAN JEH-FU
7 granted patents·2 pending applications·439 citations·filing 1995–2014
89Inventor score
Top patents by PatentIndex Score
9 records- 0186US6249898B1Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activitiesSYNOPSYS INC·Filed 1998·Granted Jun 19, 2001·80 cites·39 claims
- 0280US6577992B1Transistor level circuit simulator using hierarchical dataNASSDA CORP·Filed 1999·Granted Jun 10, 2003·133 cites·50 claims
- 0380US6311147B1Integrated circuit power net analysisSYNOPSYS INC·Filed 1998·Granted Oct 30, 2001·64 cites·20 claims
- 0480US5872952AIntegrated circuit power net analysis through simulationSYNOPSYS INC·Filed 1995·Granted Feb 16, 1999·67 cites·18 claims
- 0566US5933358AMethod and system of performing voltage drop analysis for power supply networks of VLSI circuitsSYNOPSYS INC·Filed 1997·Granted Aug 3, 1999·57 cites·22 claims
- 0661US9262571B2Layout migration with hierarchical scale and bias methodANALOG DESIGN AUTOMATION LTD G·Filed 2013·Granted Feb 16, 2016·2 cites·26 claims
- 0755US5878053AHierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designsSYNOPSYS INC·Filed 1997·Granted Mar 2, 1999·36 cites·22 claims
- 0840US2013226535A1Concurrent simulation system using graphic processing units (gpu) and method thereofTUAN JEH-FU·Filed 2012·Application pending·0 cites
- 0939US2015269297A1Methods for reducing post layout circuit simulation resultsANALOG DESIGN AUTOMATION LTD G·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →