Inventor · disambiguated record
Jinping Liu
Also filed as: LIU JINPING
100 granted patents·28 pending applications·636 citations·filing 2003–2024
99Inventor score
Files withGLOBALFOUNDRIES INC83CHARTERED SEMICONDUCTOR MFG9LIU JINPING7GLOBALFOUNDRIES US INC5CHUDZIK MICHAEL P3
Top patents by PatentIndex Score
128 records- 0197US9805982B1Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETsGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 31, 2017·19 cites·17 claims
- 0297US9455204B110 nm alternative N/P doped fin for SSRW schemeGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 27, 2016·21 cites·20 claims
- 0396US9947769B1Multiple-layer spacers for field-effect transistorsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 17, 2018·14 cites·9 claims
- 0496US9553194B1Method for improved fin profileGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 24, 2017·19 cites·16 claims
- 0596US7169675B2Material architecture for the fabrication of low temperature transistorCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Jan 30, 2007·164 cites·49 claims
- 0695US10192780B1Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masksGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 29, 2019·15 cites·20 claims
- 0795US9773680B1Advanced method for scaled SRAM with flexible active pitchGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 26, 2017·12 cites·13 claims
- 0895US7109099B2End of range (EOR) secondary defect engineering using substitutional carbon dopingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Sep 19, 2006·102 cites·20 claims
- 0994US9711447B1Self-aligned lithographic patterning with variable spacingsGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 18, 2017·15 cites·20 claims
- 1094US9159794B2Method to form wrap-around contact for finFETGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 13, 2015·15 cites·20 claims
- 1193US9761452B1Devices and methods of forming SADP on SRAM and SAQP on logicGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 12, 2017·7 cites·15 claims
- 1293US9330982B1Semiconductor device with diffusion barrier film and method of manufacturing the sameGLOBALFOUNDRIES INC·Filed 2015·Granted May 3, 2016·11 cites·20 claims
- 1393US9105497B2Methods of forming gate structures for transistor devices for CMOS applicationsGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 11, 2015·19 cites·24 claims
- 1492US10062692B1Field effect transistors with reduced parasitic resistances and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 28, 2018·18 cites·18 claims
- 1592US10002793B1Sub-fin doping methodGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 19, 2018·8 cites·16 claims
- 1692US9640423B2Integrated circuits and methods for their fabricationGLOBALFOUNDRIES INC·Filed 2015·Granted May 2, 2017·9 cites·18 claims
- 1792US9362283B2Gate structures for transistor devices for CMOS applications and productsGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 7, 2016·9 cites·20 claims
- 1891US10586860B2Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate processGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 10, 2020·6 cites·10 claims
- 1991US9589807B1Method for eliminating interlayer dielectric dishing and controlling gate height uniformityGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 7, 2017·11 cites·20 claims
- 2091US9577066B1Methods of forming fins with different fin heightsGLOBALFOUNDRIES INC·Filed 2016·Granted Feb 21, 2017·10 cites·23 claims
- 2189US10418272B1Methods, apparatus, and system for a semiconductor device comprising gates with short heightsGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 17, 2019·4 cites·14 claims
- 2289US9984933B1Silicon liner for STI CMP stop in FinFETGLOBALFOUNDRIES INC·Filed 2017·Granted May 29, 2018·7 cites·20 claims
- 2388US10347541B1Active gate contacts and method of fabrication thereofGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 9, 2019·6 cites·20 claims
- 2487US9478622B2Wrap-around contact for finFETGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 25, 2016·4 cites·18 claims
- 2586US10312150B1Protected trench isolation for fin-type field-effect transistorsGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 4, 2019·5 cites·20 claims
- 2683US10475693B1Method for forming single diffusion breaks between finFET devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Nov 12, 2019·3 cites·20 claims
- 2782US10340142B1Methods, apparatus and system for self-aligned metal hard masksGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 2, 2019·3 cites·17 claims
- 2881US8637372B2Methods for fabricating a FINFET integrated circuit on a bulk silicon substrateLIU YANXIANG·Filed 2011·Granted Jan 28, 2014·5 cites·14 claims
- 2981US8012839B2Method for fabricating a semiconductor device having an epitaxial channel and transistor having sameGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Sep 6, 2011·8 cites·7 claims
- 3080US9287180B2Integrated circuits having finFETs with improved doped channel regions and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 15, 2016·3 cites·20 claims
- 3180US8058123B2Integrated circuit and method of fabrication thereofLIU JINPING·Filed 2007·Granted Nov 15, 2011·8 cites·24 claims
- 3279US10403742B2Field-effect transistors with fins formed by a damascene-like processGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 3, 2019·2 cites·14 claims
- 3379US9570552B1Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistorsGLOBALFOUNDRIES INC·Filed 2016·Granted Feb 14, 2017·3 cites·20 claims
- 3478US11522068B2IC product comprising an insulating gate separation structure positioned between end surfaces of adjacent gate structuresGLOBALFOUNDRIES US INC·Filed 2019·Granted Dec 6, 2022·2 cites·9 claims
- 3578US10446395B1Self-aligned multiple patterning processes with layered mandrelsGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 15, 2019·2 cites·17 claims
- 3678US9991363B1Contact etch stop layer with sacrificial polysilicon layerGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 5, 2018·2 cites·19 claims
- 3777US10431500B1Multi-step insulator formation in trenches to avoid seams in insulatorsGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 1, 2019·2 cites·19 claims
- 3877US10361289B1Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the sameGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 23, 2019·2 cites·18 claims
- 3977US9704746B1Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmaskGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 11, 2017·3 cites·20 claims
- 4077US9620425B1Method of adjusting spacer thickness to provide variable threshold voltages in FinFETsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 11, 2017·2 cites·20 claims
- 4176US10453936B2Methods of forming replacement gate structures on transistor devicesGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 22, 2019·2 cites·20 claims
- 4276US10020202B2Fabrication of multi threshold-voltage devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 10, 2018·2 cites·20 claims
- 4375US9882052B2Forming defect-free relaxed SiGe finsGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 30, 2018·2 cites·15 claims
- 4475US8809962B2Transistor with reduced parasitic capacitanceLIU YANXIANG·Filed 2011·Granted Aug 19, 2014·4 cites·20 claims
- 4575US8492290B2Fabrication of silicon oxide and oxynitride having sub-nanometer thicknessCHUDZIK MICHAEL P·Filed 2011·Granted Jul 23, 2013·3 cites·20 claims
- 4675US7338886B2Implantation-less approach to fabricating strained semiconductor on isolation wafersCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Mar 4, 2008·6 cites·25 claims
- 4774US9673301B1Methods of forming spacers on FinFET devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 6, 2017·2 cites·24 claims
- 4874US9029959B2Composite high-k gate dielectric stack for reducing gate leakageBRODSKY MARYJANE·Filed 2012·Granted May 12, 2015·3 cites·12 claims
- 4971US10784195B2Electrical fuse formation during a multiple patterning processGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 22, 2020·1 cites·17 claims
- 5071US10559470B2Capping structureGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 11, 2020·1 cites·18 claims
Showing the top 50 of 128 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Jinping Liu files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →