Inventor · disambiguated record
Jiong Luo
Also filed as: LUO JIONG
8 granted patents·21 citations·filing 2016–2022
79Inventor score
Technology areasG06F
Files withSYNOPSYS INC8
Top patents by PatentIndex Score
8 records- 0191US10740517B1Integrated circuit (IC) optimization using Boolean resynthesisSYNOPSYS INC·Filed 2018·Granted Aug 11, 2020·14 cites·9 claims
- 0285US11669665B1Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimizationSYNOPSYS INC·Filed 2021·Granted Jun 6, 2023·4 cites·20 claims
- 0371US10839117B1Robust exclusive sum-of-product (ESOP) refactoringSYNOPSYS INC·Filed 2018·Granted Nov 17, 2020·2 cites·12 claims
- 0468US11010511B2Scalable boolean methods in a modern synthesis flowSYNOPSYS INC·Filed 2019·Granted May 18, 2021·1 cites·20 claims
- 0552US12175176B2Fast synthesis of logical circuit design with predictive timingSYNOPSYS INC·Filed 2022·Granted Dec 24, 2024·0 cites·17 claims
- 0649US11120184B2Satisfiability sweeping for synthesisSYNOPSYS INC·Filed 2020·Granted Sep 14, 2021·0 cites·20 claims
- 0745US10325051B2Exact delay synthesisSYNOPSYS INC·Filed 2018·Granted Jun 18, 2019·0 cites·12 claims
- 0843US10049174B2Exact delay synthesisSYNOPSYS INC·Filed 2016·Granted Aug 14, 2018·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →