Inventor · disambiguated record
Jiing-Feng Yang
Also filed as: YANG JIING-FENG
16 granted patents·3 pending applications·521 citations·filing 2001–2025
93Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD10TAIWAN SEMICONDUCTOR MFG3CHIH MING-HUI2HUANG CHENG-LIN1LIN CHUNG-YI1
Top patents by PatentIndex Score
19 records- 0197US8999839B2Semiconductor structure having an air-gap region and a method of manufacturing the sameTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Apr 7, 2015·187 cites·20 claims
- 0296US9099530B2Methods of patterning small via pitch dimensionsTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Aug 4, 2015·108 cites·20 claims
- 0395US11551968B2Inter-wire cavity for low capacitanceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jan 10, 2023·4 cites·20 claims
- 0494US10361152B2Semiconductor structure having an air-gap region and a method of manufacturing the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jul 23, 2019·11 cites·20 claims
- 0594US8728332B2Methods of patterning small via pitch dimensionsLIN CHUNG-YI·Filed 2012·Granted May 20, 2014·152 cites·19 claims
- 0691US8456009B2Semiconductor structure having an air-gap region and a method of manufacturing the sameSU SHU-HUI·Filed 2010·Granted Jun 4, 2013·19 cites·20 claims
- 0791US8304906B2Partial air gap formation for providing interconnect isolation in integrated circuitsHUANG CHENG-LIN·Filed 2010·Granted Nov 6, 2012·19 cites·20 claims
- 0879US12230603B2Method of fabricating a semiconductor chip having strength adjustment pattern in bonding layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Feb 18, 2025·0 cites·20 claims
- 0977US6495469B1High selectivity, low etch depth micro-loading process for non stop layer damascene etchTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Dec 17, 2002·20 cites·36 claims
- 1074US2025316531A1Inter-wire cavity for low capacitanceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 1173US2024395728A1Semiconductor devices and methods of manufactureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1272US2025183225A1Method of fabricating a semiconductor chipTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 1369US11756924B2Method of fabricating a semiconductor chip having strength adjustment pattern in bonding layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 12, 2023·0 cites·20 claims
- 1465US12165947B2Semiconductor devices and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Dec 10, 2024·0 cites·20 claims
- 1565US12142574B2Semiconductor devices and methods of manufactureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 12, 2024·0 cites·20 claims
- 1658US9257279B2Mask treatment for double patterning designYANG JIING-FENG·Filed 2012·Granted Feb 9, 2016·1 cites·20 claims
- 1748US12002710B2Semiconductor structure and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 4, 2024·0 cites·20 claims
- 1848US8499261B2Method and apparatus of patterning semiconductor deviceCHIH MING-HUI·Filed 2012·Granted Jul 30, 2013·0 cites·4 claims
- 1944US8196072B2Method and apparatus of patterning semiconductor deviceCHIH MING-HUI·Filed 2010·Granted Jun 5, 2012·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →