Inventor · disambiguated record
John C. Arnold
Also filed as: ARNOLD IV JOHN C · ARNOLD JOHN · ARNOLD JOHN C · ARNOLD JOHN CHRISTOPHER
71 granted patents·23 pending applications·664 citations·filing 1996–2024
99Inventor score
Top patents by PatentIndex Score
94 records- 0198US10707413B1Formation of embedded magnetic random-access memory devicesIBM·Filed 2019·Granted Jul 7, 2020·46 cites·20 claims
- 0297US8298943B1Self aligning via patterningARNOLD JOHN CHRISTOPHER·Filed 2011·Granted Oct 30, 2012·72 cites·9 claims
- 0396US8298954B1Sidewall image transfer process employing a cap material layer for a metal nitride layerARNOLD JOHN C·Filed 2011·Granted Oct 30, 2012·29 cites·20 claims
- 0496US8119531B1Mask and etch process for pattern assemblyARNOLD JOHN C·Filed 2011·Granted Feb 21, 2012·30 cites·20 claims
- 0595US8916337B2Dual hard mask lithography processARNOLD JOHN C·Filed 2012·Granted Dec 23, 2014·21 cites·25 claims
- 0694US10957850B2Multi-layer encapsulation to enable endpoint-based process control for embedded memory fabricationIBM·Filed 2018·Granted Mar 23, 2021·6 cites·18 claims
- 0794US10103022B2Alternating hardmasks for tight-pitch line formationIBM·Filed 2017·Granted Oct 16, 2018·8 cites·20 claims
- 0893US12268031B2Backside power rails and power distribution network for density scalingIBM·Filed 2021·Granted Apr 1, 2025·2 cites·12 claims
- 0993US10833257B1Formation of embedded magnetic random-access memory devices with multi-level bottom electrode via contactsIBM·Filed 2019·Granted Nov 10, 2020·8 cites·16 claims
- 1093US8883649B2Sidewall image transfer processYIN YUNPENG·Filed 2011·Granted Nov 11, 2014·27 cites·21 claims
- 1192US10685879B1Lithographic alignment of a conductive line to a viaIBM·Filed 2019·Granted Jun 16, 2020·8 cites·19 claims
- 1292US8518824B2Self aligning via patterningARNOLD JOHN CHRISTOPHER·Filed 2012·Granted Aug 27, 2013·13 cites·10 claims
- 1392US8470711B2Tone inversion with partial underlayer etch for semiconductor device formationARNOLD JOHN C·Filed 2010·Granted Jun 25, 2013·11 cites·12 claims
- 1492US5683548AInductively coupled plasma reactor and processMOTOROLA INC·Filed 1996·Granted Nov 4, 1997·158 cites·28 claims
- 1590US10032632B2Selective gas etching for self-aligned pattern transferIBM·Filed 2016·Granted Jul 24, 2018·4 cites·19 claims
- 1690US7923712B2Phase change memory element with a peripheral connection to a thin film electrodeIBM·Filed 2009·Granted Apr 12, 2011·17 cites·20 claims
- 1789US8470706B2Methods to mitigate plasma damage in organosilicate dielectricsARNOLD JOHN C·Filed 2012·Granted Jun 25, 2013·8 cites·15 claims
- 1887US10833258B1MRAM device formation with in-situ encapsulationIBM·Filed 2019·Granted Nov 10, 2020·3 cites·13 claims
- 1986US8084329B2Transistor devices and methods of makingARNOLD JOHN C·Filed 2010·Granted Dec 27, 2011·8 cites·13 claims
- 2085US8383483B2High performance CMOS circuits, and methods for fabricating sameIBM·Filed 2009·Granted Feb 26, 2013·10 cites·15 claims
- 2185US7781332B2Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacerIBM·Filed 2007·Granted Aug 24, 2010·11 cites·14 claims
- 2284US8481423B2Methods to mitigate plasma damage in organosilicate dielectricsARNOLD JOHN C·Filed 2007·Granted Jul 9, 2013·8 cites·20 claims
- 2383US10580652B2Alternating hardmasks for tight-pitch line formationIBM·Filed 2018·Granted Mar 3, 2020·2 cites·20 claims
- 2481US11239077B2Litho-etch-litho-etch with self-aligned blocksIBM·Filed 2019·Granted Feb 1, 2022·2 cites·20 claims
- 2581US8129843B2Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacerARNOLD JOHN C·Filed 2010·Granted Mar 6, 2012·5 cites·5 claims
- 2681US7550313B2Method for delineation of phase change memory (PCM) cells separated by PCM and upper electrode regions modified to have high film resistivityIBM·Filed 2007·Granted Jun 23, 2009·19 cites·10 claims
- 2780US11189528B2Subtractive RIE interconnectIBM·Filed 2020·Granted Nov 30, 2021·1 cites·20 claims
- 2879US12488986B2Selective gas etching for self-aligned pattern transferADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Dec 2, 2025·0 cites·10 claims
- 2979US8586482B2Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formationARNOLD JOHN C·Filed 2011·Granted Nov 19, 2013·4 cites·20 claims
- 3078US8735283B2Method for forming small dimension openings in the organic masking layer of tri-layer lithographyARNOLD JOHN C·Filed 2011·Granted May 27, 2014·4 cites·33 claims
- 3178US8580692B2Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formationARNOLD JOHN C·Filed 2011·Granted Nov 12, 2013·4 cites·18 claims
- 3276US11302533B2Selective gas etching for self-aligned pattern transferTESSERA INC·Filed 2021·Granted Apr 12, 2022·0 cites·20 claims
- 3375US6500315B1Method and apparatus for forming a layer on a substrateMOTOROLA INC·Filed 2000·Granted Dec 31, 2002·15 cites·23 claims
- 3472US8536031B2Method of fabricating dual damascene structures using a multilevel multiple exposure patterning schemeARNOLD JOHN C·Filed 2010·Granted Sep 17, 2013·2 cites·11 claims
- 3571US8168542B2Methods of forming tubular objectsCHEN KUAN-NENG·Filed 2008·Granted May 1, 2012·2 cites·19 claims
- 3670US6054377AMethod for forming an inlaid via in a semiconductor deviceMOTOROLA INC·Filed 1997·Granted Apr 25, 2000·38 cites·20 claims
- 3769US12243771B2Selective patterning of vias with hardmasksIBM·Filed 2022·Granted Mar 4, 2025·0 cites·19 claims
- 3869US11830807B2Placing top vias at line ends by selective growth of via mask from line cut dielectricIBM·Filed 2021·Granted Nov 28, 2023·0 cites·6 claims
- 3968US10930504B2Selective gas etching for self-aligned pattern transferTESSERA INC·Filed 2019·Granted Feb 23, 2021·0 cites·20 claims
- 4067US11171002B2Alternating hardmasks for tight-pitch line formationTESSERA INC·Filed 2020·Granted Nov 9, 2021·0 cites·16 claims
- 4167US7880241B2Low-temperature electrically activated gate electrode and method of fabricating sameIBM·Filed 2007·Granted Feb 1, 2011·2 cites·19 claims
- 4266US10714683B2Multilayer hardmask for high performance MRAM devicesIBM·Filed 2019·Granted Jul 14, 2020·0 cites·17 claims
- 4365US8012811B2Methods of forming features in integrated circuitsIBM·Filed 2008·Granted Sep 6, 2011·2 cites·18 claims
- 4464US10559467B2Selective gas etching for self-aligned pattern transferIBM·Filed 2018·Granted Feb 11, 2020·0 cites·20 claims
- 4563US2025391756A1Self-aligned via connection with enlarged contact area to subtractive lineIBM·Filed 2024·Application pending·0 cites
- 4662US12489035B2Semiconductor passive device integration for silicon-on-insulator substrateIBM·Filed 2023·Granted Dec 2, 2025·0 cites·20 claims
- 4761US11688636B2Spin on scaffold film for forming topviaIBM·Filed 2021·Granted Jun 27, 2023·0 cites·20 claims
- 4861US7776695B2Semiconductor device structure having low and high performance devices of same conductive type on same substrateIBM·Filed 2006·Granted Aug 17, 2010·2 cites·17 claims
- 4961US2025386559A1Dielectric liner protection to prevent shorting to gateIBM·Filed 2024·Application pending·0 cites
- 5061US2025226319A1Interconnect with topviaIBM·Filed 2024·Application pending·0 cites
Showing the top 50 of 94 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →