Inventor · disambiguated record
John Barnak
Also filed as: BARNAK JOHN · BARNAK JOHN P
17 granted patents·6 pending applications·761 citations·filing 1998–2005
96Inventor score
Top patents by PatentIndex Score
23 records- 0198US7022559B2MOSFET gate electrodes having performance tuned work functions and methods of making sameINTEL CORP·Filed 2002·Granted Apr 4, 2006·216 cites·22 claims
- 0297US7316949B2Integrating n-type and p-type metal gate transistorsINTEL CORP·Filed 2005·Granted Jan 8, 2008·50 cites·13 claims
- 0396US6858483B2Integrating n-type and p-type metal gate transistorsINTEL CORP·Filed 2002·Granted Feb 22, 2005·81 cites·8 claims
- 0495US6696327B1Method for making a semiconductor device having a high-k gate dielectricINTEL CORP·Filed 2003·Granted Feb 24, 2004·85 cites·2 claims
- 0594US6972225B2integrating n-type and P-type metal gate transistorsINTEL CORP·Filed 2004·Granted Dec 6, 2005·54 cites·19 claims
- 0694US6953719B2Integrating n-type and p-type metal gate transistorsINTEL CORP·Filed 2004·Granted Oct 11, 2005·62 cites·9 claims
- 0792US6709911B1Method for making a semiconductor device having a high-k gate dielectricINTEL CORP·Filed 2003·Granted Mar 23, 2004·64 cites·17 claims
- 0883US6855639B1Precise patterning of high-K filmsINTEL CORP·Filed 2003·Granted Feb 15, 2005·29 cites·32 claims
- 0979US7064446B2Under bump metallization layer to enable use of high tin content solder bumpsINTEL CORP·Filed 2004·Granted Jun 20, 2006·29 cites·6 claims
- 1078US6939815B2Method for making a semiconductor device having a high-k gate dielectricINTEL CORP·Filed 2003·Granted Sep 6, 2005·20 cites·14 claims
- 1178US6806146B1Method for making a semiconductor device having a high-k gate dielectricINTEL CORP·Filed 2003·Granted Oct 19, 2004·21 cites·4 claims
- 1276US6897134B2Method for making a semiconductor device having a high-k gate dielectricINTEL CORP·Filed 2003·Granted May 24, 2005·17 cites·2 claims
- 1375US6867102B2Method for making a semiconductor device having a high-k gate dielectricINTEL CORP·Filed 2004·Granted Mar 15, 2005·16 cites·6 claims
- 1463US6849509B2Methods of forming a multilayer stack alloy for work function engineeringINTEL CORP·Filed 2002·Granted Feb 1, 2005·10 cites·23 claims
- 1557US7122870B2Methods of forming a multilayer stack alloy for work function engineeringINTEL CORP·Filed 2004·Granted Oct 17, 2006·7 cites·14 claims
- 1642US7087521B2Forming an intermediate layer in interconnect joints and structures formed therebyINTEL CORP·Filed 2004·Granted Aug 8, 2006·0 cites·36 claims
- 1741US7567379B2Technique to prevent tin contamination of mirrors and electrodes in an EUV lithography systemINTEL CORP·Filed 2004·Granted Jul 28, 2009·0 cites·10 claims
- 1841US2005233530A1Enhanced gate structureBARNAK JOHN P·Filed 2005·Application pending·0 cites
- 1940US2005110072A1Precise patterning of high-K filmsFiled 2004·Application pending·0 cites
- 2040US2005250323A1Under bump metallization layer to enable use of high tin content solder bumpsBARNAK JOHN P·Filed 2005·Application pending·0 cites
- 2138US2005017238A1Forming a high dielectric constant film using metallic precursorFiled 2003·Application pending·0 cites
- 2235US2005045961A1Enhanced gate structureFiled 2003·Application pending·0 cites
- 2330US2002008257A1Mosfet gate electrodes having performance tuned work functions and methods of making sameFiled 1998·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when John Barnak files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →