US2005250323A1PendingUtilityA1

Under bump metallization layer to enable use of high tin content solder bumps

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Assignee: BARNAK JOHN PPriority: Mar 29, 2004Filed: Jul 13, 2005Published: Nov 10, 2005
Est. expiryMar 29, 2024(expired)· nominal 20-yr term from priority
H10W 72/9415H10W 72/9226H10W 72/923H10W 72/252H10W 72/251H10W 72/019H10W 72/012H10W 72/00
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Claims

Abstract

Apparatus and methods of fabricating an under bump metallization structure including an adhesion layer abutting a conductive pad, a molybdenum-containing barrier layer abutting the adhesion layer, a wetting layer abutting the molybdenum-containing barrier layer, and high tin content solder material abutting the wetting layer. The wetting layer may be substantially subsumed in the high content solder forming an intermetallic compound layer. The molybdenum-containing barrier layer prevents the movement of tin in the high tin content solder material from migrating to dielectric layers abutting the conductive pad and potentially causing delamination and/or attacking any underlying structures, particularly copper structures, which may be present.

Claims

exact text as granted — not AI-modified
1 - 6 . (canceled)  
   
   
       7 . A method comprising: 
 providing at least one interlayer dielectric having at least one abutting conductive pad;    forming an adhesion layer on at least a portion of said at least one conductive pad;    forming a molybdenum-containing barrier layer on at least a portion of said adhesion layer;    forming a wetting layer on at least a portion of said molybdenum-containing barrier layer; and    forming a high tin content solder plug on at least a portion of said wetting layer, said high tin content solder material having a least about 75% tin by weight.    
   
   
       8 . The method of  claim 7 , wherein forming said molybdenum-containing barrier layer comprises forming a molybdenum-containing barrier layer containing at least about 90% (atomic) molybdenum.  
   
   
       9 . The method of  claim 7 , wherein forming said high tin content solder plug comprises a high tin content solder plug containing at least about 90% (by weight) tin.  
   
   
       10 . The method of  claim 7 , further comprising said conductive pad abutting at least one layer of low k dielectric material.  
   
   
       11 . The method of  claim 7 , wherein providing at least one interlayer dielectric comprises providing at least one layer of carbon doped oxide.  
   
   
       12 . The method of  claim 7 , further comprising reflowing said high tin content solder plug to from a solder bump.  
   
   
       13 . The method of  claim 12 , wherein said wetting layer is substantially subsumed into said high tin content solder bump during said reflow.  
   
   
       14 . The method of  claim 7 , wherein forming said molybdenum-containing barrier layer comprises sputter depositing a molybdenum-containing material.  
   
   
       15 . An electronic system, comprising: 
 an external substrate within a housing; and    at least one microelectronic device package attached to said external substrate, having at least one under bump metallization layer including:    an adhesion layer abutting a conductive pad;    a molybdenum-containing barrier layer abutting said adhesion layer;    a wetting layer abutting said molybdenum-containing barrier layer; and    high tin content solder material abutting said wetting layer, said high tin content solder material having a least about 75% tin by weight; and    an input device interfaced with said external substrate; and    a display device interfaced with said external substrate.    
   
   
       16 . The system of  claim 15 , wherein said molybdenum-containing barrier layer comprises a material containing at least about 90% (atomic) molybdenum.  
   
   
       17 . The system of  claim 15 , wherein said high tin content solder material comprises a material containing at least about 90% (by weight) tin.  
   
   
       18 . The system of  claim 15 , further comprising said conductive pad abutting at least one layer of low k dielectric material.  
   
   
       19 . The system of  claim 18 , wherein said at least one layer of low-k dielectric material comprises at least one layer of carbon doped oxide.  
   
   
       20 . The system of  claim 15 , wherein said wetting layer is substantially subsumed in said high tin content solder material forming an intermetallic compound layer.

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