Inventor · disambiguated record
Seshu V. Sattiraju
Also filed as: SATTIRAJU SESHU V
4 granted patents·3 pending applications·64 citations·filing 2004–2017
76Inventor score
Technology areasH10W
Top patents by PatentIndex Score
7 records- 0192US9142510B23D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approachLEE KEVIN J·Filed 2011·Granted Sep 22, 2015·17 cites·19 claims
- 0291US9449913B23D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon viasLEE KEVIN J·Filed 2011·Granted Sep 20, 2016·18 cites·22 claims
- 0379US7064446B2Under bump metallization layer to enable use of high tin content solder bumpsINTEL CORP·Filed 2004·Granted Jun 20, 2006·29 cites·6 claims
- 0448US9530740B23D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approachINTEL CORP·Filed 2015·Granted Dec 27, 2016·0 cites·20 claims
- 0540US2005250323A1Under bump metallization layer to enable use of high tin content solder bumpsBARNAK JOHN P·Filed 2005·Application pending·0 cites
- 0637US2021057348A1Barrier materials between bumps and padsINTEL CORP·Filed 2017·Application pending·0 cites
- 0732US2019237391A1Chip assemblies employing solder bonds to back-side lands including an electrolytic nickel layerINTEL CORP·Filed 2016·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Seshu V. Sattiraju files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →