Inventor · disambiguated record
Joerg Grosse
Also filed as: GROSSE JOERG
16 granted patents·1 pending application·60 citations·filing 2005–2020
92Inventor score
Files withBreker Verification Systems12GROSSE JOERG2ONESPIN SOLUTIONS GMBH1SPRINGSOFT USA INC1SYNOPSYS INC1
Top patents by PatentIndex Score
17 records- 0194US9316689B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2015·Granted Apr 19, 2016·13 cites·20 claims
- 0290US9874608B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2017·Granted Jan 23, 2018·5 cites·20 claims
- 0388US9651619B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2016·Granted May 16, 2017·4 cites·27 claims
- 0488US8468503B2Method for testing a computer programGROSSE JOERG·Filed 2007·Granted Jun 18, 2013·23 cites·20 claims
- 0587US10365326B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2018·Granted Jul 30, 2019·3 cites·30 claims
- 0682US9689921B2Testing SoC with portable scenario models and at different levelsBreker Verification Systems·Filed 2016·Granted Jun 27, 2017·2 cites·30 claims
- 0781US9310433B2Testing SOC with portable scenario models and at different levelsBreker Verification Systems·Filed 2015·Granted Apr 12, 2016·2 cites·22 claims
- 0874US11748240B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2020·Granted Sep 5, 2023·0 cites·19 claims
- 0968US11055212B2Testing SoC with portable scenario models and at different levelsBreker Verification Systems·Filed 2019·Granted Jul 6, 2021·0 cites·26 claims
- 1068US10838006B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2019·Granted Nov 17, 2020·0 cites·27 claims
- 1168US8311793B2Method for evaluating a test program qualityGROSSE JOERG·Filed 2005·Granted Nov 13, 2012·5 cites·15 claims
- 1263US9342645B2Method for testing a computer programSYNOPSYS INC·Filed 2013·Granted May 17, 2016·1 cites·24 claims
- 1362US10429442B2Testing SOC with portable scenario models and at different levelsBreker Verification Systems·Filed 2017·Granted Oct 1, 2019·0 cites·24 claims
- 1460US11113184B2Display in a graphical format of test results generated using scenario modelsBreker Verification Systems·Filed 2016·Granted Sep 7, 2021·0 cites·22 claims
- 1560US8010919B2Method for evaluating the quality of a computer programSPRINGSOFT USA INC·Filed 2005·Granted Aug 30, 2011·2 cites·8 claims
- 1658US9360523B2Display in a graphical format of test results generated using scenario modelsBreker Verification Systems·Filed 2015·Granted Jun 7, 2016·0 cites·3 claims
- 1734US2018364298A1System and method for formal circuit verificationONESPIN SOLUTIONS GMBH·Filed 2017·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Joerg Grosse files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →