Inventor · disambiguated record
John W. Hagerman
Also filed as: HAGERMAN JOHN · HAGERMAN JOHN W
3 granted patents·58 citations·filing 1998–2019
71Inventor score
Technology areasG06F
Top patents by PatentIndex Score
3 records- 0173US10643012B1Concurrent formal verification of logic synthesisSYNOPSYS INC·Filed 2019·Granted May 5, 2020·3 cites·21 claims
- 0254US6530072B1Rule based hierarchy generation in a circuit design verification systemCHRYSALIS SYMBOLIC DESIGN INC·Filed 1999·Granted Mar 4, 2003·39 cites·22 claims
- 0336US6219821B1Computers systems and methods for verifying representations of a circuit designCHRYSALIS SYMBOLIC DESIGN INC·Filed 1998·Granted Apr 17, 2001·16 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →