Inventor · disambiguated record
Jonathan Haigh
Also filed as: HAIGH JONATHAN · HAIGH JONATHAN R
95 granted patents·1 pending application·204 citations·filing 2013–2019
99Inventor score
Top patents by PatentIndex Score
96 records- 0198US10593604B1Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Mar 17, 2020·19 cites·19 claims
- 0298US9870962B1Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Jan 16, 2018·13 cites·19 claims
- 0398US9799575B2Integrated circuit containing DOEs of NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Oct 24, 2017·19 cites·11 claims
- 0497US9805994B1Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such padsPDF SOLUTIONS INC·Filed 2016·Granted Oct 31, 2017·15 cites·18 claims
- 0597US9627370B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Apr 18, 2017·15 cites·20 claims
- 0696US10978438B1IC with test structures and E-beam pads embedded within a contiguous standard cell areaPDF SOLUTIONS INC·Filed 2019·Granted Apr 13, 2021·9 cites·14 claims
- 0795US9595536B1Standard cell library that includes 13-CPP and 17-CPP D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacenciesPDF SOLUTIONS INC·Filed 2016·Granted Mar 14, 2017·13 cites·27 claims
- 0894US9461065B1Standard cell library with DFM-optimized M0 cuts and V0 adjacenciesPDF SOLUTIONS INC·Filed 2016·Granted Oct 4, 2016·10 cites·25 claims
- 0993US9741703B1Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Aug 22, 2017·4 cites·20 claims
- 1093US9691672B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Jun 27, 2017·4 cites·20 claims
- 1193US9627371B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Apr 18, 2017·7 cites·20 claims
- 1290US10199288B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areasPDF SOLUTIONS INC·Filed 2018·Granted Feb 5, 2019·2 cites·20 claims
- 1390US10199283B1Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stagePDF SOLUTIONS INC·Filed 2017·Granted Feb 5, 2019·3 cites·20 claims
- 1490US9905487B1Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opensPDF SOLUTIONS INC·Filed 2016·Granted Feb 27, 2018·3 cites·10 claims
- 1589US9786648B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Oct 10, 2017·2 cites·20 claims
- 1689US9773773B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Sep 26, 2017·2 cites·20 claims
- 1789US9761575B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Sep 12, 2017·2 cites·20 claims
- 1887US10290552B1Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stagePDF SOLUTIONS INC·Filed 2018·Granted May 14, 2019·2 cites·20 claims
- 1987US10199294B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stagePDF SOLUTIONS INC·Filed 2018·Granted Feb 5, 2019·1 cites·20 claims
- 2087US9761573B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Sep 12, 2017·2 cites·20 claims
- 2187US9529954B1Standard cell library with DFM-optimized M0 cutsPDF SOLUTIONS INC·Filed 2016·Granted Dec 27, 2016·6 cites·20 claims
- 2286US10096530B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Oct 9, 2018·4 cites·14 claims
- 2386US9627408B1D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacenciesPDF SOLUTIONS INC·Filed 2016·Granted Apr 18, 2017·4 cites·27 claims
- 2485US9947601B1Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Apr 17, 2018·1 cites·19 claims
- 2585US9202820B1Flip-flop, latch, and mux cells for use in a standard cell library and integrated circuits made therefromPDF SOLUTIONS INC·Filed 2014·Granted Dec 1, 2015·7 cites·10 claims
- 2684US9922968B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Mar 20, 2018·1 cites·23 claims
- 2784US9773774B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Sep 26, 2017·4 cites·17 claims
- 2884US9721937B1Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Aug 1, 2017·1 cites·23 claims
- 2983US9653446B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted May 16, 2017·2 cites·20 claims
- 3082US9984970B1Advanced node standard logic cells that utilizes TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogsPDF SOLUTIONS INC·Filed 2017·Granted May 29, 2018·3 cites·6 claims
- 3182US9870441B1Snap-to valid pattern system and methodPDF SOLUTIONS INC·Filed 2016·Granted Jan 16, 2018·3 cites·7 claims
- 3281US9704846B1IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the samePDF SOLUTIONS INC·Filed 2016·Granted Jul 11, 2017·4 cites·7 claims
- 3380US9911649B1Process for making and using mesh-style NCEM padsPDF SOLUTIONS INC·Filed 2016·Granted Mar 6, 2018·2 cites·3 claims
- 3480US9728553B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Aug 8, 2017·1 cites·20 claims
- 3579US9831141B1Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Nov 28, 2017·1 cites·20 claims
- 3679US9711421B1Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Jul 18, 2017·1 cites·20 claims
- 3776US9929063B1Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Mar 27, 2018·2 cites·19 claims
- 3876US9768083B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Sep 19, 2017·2 cites·16 claims
- 3976US9646961B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted May 9, 2017·1 cites·20 claims
- 4074US10199284B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and chamfer short test areasPDF SOLUTIONS INC·Filed 2018·Granted Feb 5, 2019·0 cites·20 claims
- 4173US10109539B1Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Oct 23, 2018·0 cites·19 claims
- 4273US9922890B1Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Mar 20, 2018·0 cites·19 claims
- 4373US9911669B1Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Mar 6, 2018·0 cites·19 claims
- 4473US9911668B1Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Mar 6, 2018·0 cites·19 claims
- 4573US9911670B1Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatePDF SOLUTIONS INC·Filed 2017·Granted Mar 6, 2018·0 cites·19 claims
- 4673US9899276B1Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Feb 20, 2018·0 cites·19 claims
- 4773US9881843B1Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Jan 30, 2018·0 cites·19 claims
- 4872US10269786B1Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Apr 23, 2019·0 cites·19 claims
- 4972US10211112B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areasPDF SOLUTIONS INC·Filed 2018·Granted Feb 19, 2019·0 cites·20 claims
- 5072US10199289B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areasPDF SOLUTIONS INC·Filed 2018·Granted Feb 5, 2019·0 cites·20 claims
Showing the top 50 of 96 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →