Inventor · disambiguated record
John R. Hauser
Also filed as: HAUSER JOHN R · HAUSER JOHN R JR · HAUSER JOHN REID · HAUSER JR JOHN REID
7 granted patents·3 pending applications·341 citations·filing 1985–2013
89Inventor score
Files with3PLUS1 TECHNOLOGY INC2RAMCHANDRAN AMIT2UNIV NORTH CAROLINA STATE2ADVANCED MICRO DEVICES INC1DIEHL NAGLE SHERRA E1
Top patents by PatentIndex Score
10 records- 0193US8386751B2Low power, high performance, heterogeneous, scalable processor architectureICELERO LLC·Filed 2010·Granted Feb 26, 2013·38 cites·18 claims
- 0293US7721069B2Low power, high performance, heterogeneous, scalable processor architecture3PLUS1 TECHNOLOGY INC·Filed 2005·Granted May 18, 2010·56 cites·36 claims
- 0391US5418885AThree-zone rapid thermal processing system utilizing wafer edge heating meansUNIV NORTH CAROLINA STATE·Filed 1992·Granted May 23, 1995·92 cites·19 claims
- 0489US6472233B1MOSFET test structure for capacitance-voltage measurementsADVANCED MICRO DEVICES INC·Filed 2000·Granted Oct 29, 2002·45 cites·12 claims
- 0583US4805148AHigh impendance-coupled CMOS SRAM for improved single event immunityDIEHL NAGLE SHERRA E·Filed 1985·Granted Feb 14, 1989·75 cites·11 claims
- 0681US8880850B2Low power, high performance, heterogeneous, scalable processor architectureICELERO INC·Filed 2013·Granted Nov 4, 2014·5 cites·12 claims
- 0757US5253324AConical rapid thermal processing apparatusUNIV NORTH CAROLINA STATE·Filed 1992·Granted Oct 12, 1993·30 cites·31 claims
- 0849US2007294511A1Programmable Processor Architecture3PLUS1 TECHNOLOGY INC·Filed 2007·Application pending·0 cites
- 0948US2006026578A1Programmable processor architecture hirarchical compilationRAMCHANDRAN AMIT·Filed 2005·Application pending·0 cites
- 1037US2007198901A1Configurable interface for connecting various chipsets for wireless communication to a programmable (multi-)processorRAMCHANDRAN AMIT·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →