Programmable processor architecture hirarchical compilation

Abstract

One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits or greater in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W. A scenario compiler is included in a hierarchical flow of compilation and used with other compilation and assembler blocks to generate binary code based on different types of codes to allow for efficient processing based on the sub-processors while maintaining low power consumption when the binary code is executed.

1 . A software architecture for execution on a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits, or more, in parallel, W being an integer value and having at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value and smaller than, the software architecture comprising: 
 a scenario compiler for pre-compiling a scenario to create a binary code based on assembly code and high level language and scenario description language code, the scenario compiler including a plurality of applications, each application including one or more kernels, the scenario compiler pre-compiling the scenario for efficient execution thereof by a plurality of sub-processors, each sub-processor including a control circuit including high level code for execution thereof, the control circuit is a high language programmable controller for the sub-processor,    wherein a hierarchical compilation of different types of programming codes allow for efficient binary code creating while reducing power consumption when the binary code is executed by the sub-processors.    
   
   
       2 . A software architecture, as recited in  claim 1 , further including a schedule and synchronization block communicating with the scenario compiler and for generating code, based on scenario description language (SDL) to operate with one or more of the sub-processors.  
   
   
       3 . A software architecture, as recited in  claim 2 , further including a high level language compiler block receiving input from the synchronization block for compiling high level code.  
   
   
       4 . A software architecture, as recited in  claim 3 , further including an assembler block coupled to receive information from the high level language compiler block and from an assembly code block, which provides assembly code written by a user, the assembler block for assembling the assembly code and the information received from the high level language compiler block.  
   
   
       5 . A software architecture, as recited in  claim 4 , further including a binary code block for generating binary code based on assembly code, high level code and SDL.  
   
   
       6 . A software architecture, as recited in  claim 5 , further including a scenario description and optional optimization block coupled to the scenario description block and upon the generation of binary code, a user's design goals are verified and if the design goals are not met, the scenario description and optional optimization block modifies the scenario.  
   
   
       7 . A software architecture, as recited in  claim 6 , wherein the sub-processors each include applications having kernels, the kernels being engines for execution of computationally intensive code.  
   
   
       8 . A software architecture, as recited in  claim 7 , further including a scenario description block coupled to the scenario compiler block for generating SDL for describing inter-dependencies between the kernals.  
   
   
       9 . A software architecture, as recited in  claim 8 , further including a low-level assembler and linker block coupled to the optimizing assembler block for assembling the lowest-level code.  
   
   
       10 . A software architecture, as recited in  claim 9 , wherein the low-level assembler and linker block further includes a latency verification block responsive to an N number of previous instructions and a current instruction for verifying the presence of N number of previous instructions used by a user for instructions requiring previous instructions.  
   
   
       11 . A software architecture, as recited in  claim 10 , wherein the latency verification block for verifying the user's instruction, which includes use of previous instructions, against latency rules.  
   
   
       12 . A software architecture, as recited in  claim 11 , further including shared memory coupled to the sub-processors wherein the kernel of one of the sub-processors hands off to another sub-processor by placing, in the shared memory, information to be used by the another sub-processor.  
   
   
       13 . A method of generating and executing code on a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits, or more, in parallel, W being an integer value and having at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value and smaller than, the software architecture comprising: 
 pre-compiling a scenario to create a binary code based on assembly code and high level language and scenario description language code;    generating efficient binary code to be executed by the sub-processors based on applications including kernels, the kernels for executing computationally intensive code, the execution of the binary code by the sub-processors causing reduction of power consumption and flexible coding options to a user.    
   
   
       14 . A method of generating and executing code, as recited in  claim 13 , further including performing latency verification to prevent a user from using erroneous previous instructions.