Inventor · disambiguated record
Joseph J. Jamann
Also filed as: JAMANN JOSEPH · JAMANN JOSEPH J
9 granted patents·2 pending applications·43 citations·filing 2009–2012
87Inventor score
Top patents by PatentIndex Score
11 records- 0189US8024694B2Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristicsAGERE SYSTEMS INC·Filed 2009·Granted Sep 20, 2011·10 cites·7 claims
- 0285US8307324B2Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristicsJAMANN JOSEPH J·Filed 2011·Granted Nov 6, 2012·6 cites·6 claims
- 0384US8341573B2Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flowRAO VISHWAS M·Filed 2010·Granted Dec 25, 2012·8 cites·7 claims
- 0484US8281266B2Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed therebyJAMANN JOSEPH J·Filed 2009·Granted Oct 2, 2012·8 cites·15 claims
- 0582US8543951B2Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flowLSI CORP·Filed 2012·Granted Sep 24, 2013·6 cites·18 claims
- 0670US8539423B2Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristicsAGERE SYSTEMS LLC·Filed 2012·Granted Sep 17, 2013·1 cites·10 claims
- 0766US8694937B2Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the sameLSI CORP·Filed 2012·Granted Apr 8, 2014·2 cites·14 claims
- 0863US8522179B1System and method for managing timing margin in a hierarchical integrated circuit design processGRIESBACH WILLIAM R·Filed 2012·Granted Aug 27, 2013·2 cites·20 claims
- 0948US2013055175A1Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed therebyJAMANN JOSEPH J·Filed 2012·Application pending·0 cites
- 1045US8332792B2Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the sameTETELBAUM ALEXANDER·Filed 2010·Granted Dec 11, 2012·0 cites·16 claims
- 1141US2014059505A1Method for designing integrated circuits employing correct-by-construction progressive modeling and an apparatus employing the methodBLAIR GERARD M·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →