Inventor · disambiguated record
Joseph Karniewicz
Also filed as: KARNIEWICZ JOSEPH · KARNIEWICZ JOSEPH J
17 granted patents·2 pending applications·1,144 citations·filing 1990–2006
96Inventor score
Files withMICRON TECHNOLOGY INC19
Top patents by PatentIndex Score
19 records- 0197US5134085AReduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memoriesMICRON TECHNOLOGY INC·Filed 1991·Granted Jul 28, 1992·426 cites·23 claims
- 0296US5780906AStatic memory cell and method of manufacturing a static memory cellMICRON TECHNOLOGY INC·Filed 1997·Granted Jul 14, 1998·184 cites·14 claims
- 0392US6404018B1Static memory cell and method of manufacturing a static memory cellMICRON TECHNOLOGY INC·Filed 2000·Granted Jun 11, 2002·72 cites·12 claims
- 0492US5057449AProcess for creating two thicknesses of gate oxide within a dynamic random access memoryMICRON TECHNOLOGY INC·Filed 1990·Granted Oct 15, 1991·104 cites·3 claims
- 0591US6184539B1Static memory cell and method of forming static memory cellMICRON TECHNOLOGY INC·Filed 1998·Granted Feb 6, 2001·75 cites·30 claims
- 0687US5135882ATechnique for forming high-value inter-nodal coupling resistance for rad-hard applications in a double-poly, salicide process using local interconnectMICRON TECHNOLOGY INC·Filed 1991·Granted Aug 4, 1992·74 cites·5 claims
- 0781US5976926AStatic memory cell and method of manufacturing a static memory cellMICRON TECHNOLOGY INC·Filed 1997·Granted Nov 2, 1999·38 cites·27 claims
- 0877US5030585ASplit-polysilicon CMOS DRAM process incorporating selective self-aligned silicidation of conductive regions and nitride blanket protection of N-channel regions during P-channel gate spacer formationMICRON TECHNOLOGY INC·Filed 1990·Granted Jul 9, 1991·45 cites·18 claims
- 0971US7096446B2Hierarchical semiconductor designMICRON TECHNOLOGY INC·Filed 2002·Granted Aug 22, 2006·11 cites·15 claims
- 1070US5026657ASplit-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates, and N+ regionsMICRON TECHNOLOGY INC·Filed 1990·Granted Jun 25, 1991·33 cites·10 claims
- 1163US5757051AStatic memory cell and method of manufacturing a static memory cellMICRON TECHNOLOGY INC·Filed 1996·Granted May 26, 1998·17 cites·34 claims
- 1262US5672536AMethod of manufacturing a novel static memory cell having a tunnel diodeMICRON TECHNOLOGY INC·Filed 1996·Granted Sep 30, 1997·16 cites·30 claims
- 1360US5629546AStatic memory cell and method of manufacturing a static memory cellMICRON TECHNOLOGY INC·Filed 1995·Granted May 13, 1997·16 cites·10 claims
- 1456US5770497AMethod of manufacturing a novel static memory cell having a tunnel diodeMICRON TECHNOLOGY INC·Filed 1997·Granted Jun 23, 1998·12 cites·13 claims
- 1551US2006253809A1Hierarchial semiconductor designMICRON TECHNOLOGY INC·Filed 2006·Application pending·0 cites
- 1651US2006253827A1Hierarchial semiconductor designMICRON TECHNOLOGY INC·Filed 2006·Application pending·0 cites
- 1747US6449757B1Hierarchical semiconductor designMICRON TECHNOLOGY INC·Filed 1998·Granted Sep 10, 2002·13 cites·23 claims
- 1837US6140685AStatic memory cell and method of manufacturing a static memory cellMICRON TECHNOLOGY INC·Filed 1999·Granted Oct 31, 2000·3 cites·12 claims
- 1933US6922659B2Parameter population of cells of a hierarchical semiconductor structure via file relationMICRON TECHNOLOGY INC·Filed 1998·Granted Jul 26, 2005·5 cites·36 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →