Hierarchial semiconductor design

Abstract

Hierarchical semiconductor structure design is disclosed. One aspect of the invention is a computerized system that includes a semiconductor structure (such as a semiconductor test structure) and a basic atom. The system also includes a hierarchy of abstractions ordered from highest to lowest. Each abstraction relates a plurality of instances of an immediately lower abstraction; the highest abstraction corresponds to the structure, and the lowest abstraction corresponds to the basic atom. A plurality of sets of parameters also is included within the system, where each set of parameters corresponds to an instance of an abstraction. Changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.

1 . A computer comprising: 
 a processor;    a first computer-readable medium; and,    a computer program executed by the processor from the first computer-readable medium to provide for hierarchical semiconductor structure design utilizing a basic atom.    
   
   
       2 . The computer of  claim 1 , wherein the semiconductor structure design comprises a semiconductor test structure design.  
   
   
       3 . The computer of  claim 1 , wherein the program provides for a hierarchy of abstractions ordered from highest to lowest; wherein the lowest abstraction corresponding to the basic atom; and wherein the highest abstraction corresponding to the structure.  
   
   
       4 . The computer of  claim 3 , wherein each abstraction relates a plurality of instances of an immediately lower abstraction.  
   
   
       5 . The computer of  claim 4 , wherein each instance of an abstraction has a set of parameters such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.  
   
   
       6 . The computer of  claim 4 , wherein each instance of an abstraction has a set of parameters such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of all lower abstractions.  
   
   
       7 . The computer of  claim 4 , wherein each instance of an abstraction has a set of parameters; and wherein the set of parameters associated with an instance of an abstraction convey information related to physical characteristics of the abstraction.  
   
   
       8 . The computer of  claim 7 , wherein the information related to physical characteristics of the abstraction includes at least one of: 
 grid placement information relating to the overall grid requirements of the semiconductor fabrication technology;    physical location of the instance of the abstraction, with respect to the overall grid requirement;    physical location of the instance of the abstraction, with respect to other instances of the abstraction;    electrical characteristics of the instance of the abstraction;    electrical characteristic limitation of required by the semiconductor fabrication technology;    power consumption of the instances of the abstraction;    density of the instances of the abstraction;    physical size of the instances of the abstraction;    connectivity information of the instance of the abstraction with respect to other instances of abstractions; and    requirements specific to a particular instance of the abstraction.    
   
   
       9 . The computer of  claim 1 , wherein the semiconductor structure design comprises a semiconductor chip structure design.  
   
   
       10 . The computer of  claim 1 , wherein the computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.  
   
   
       11 . A computer comprising: 
 a processor;    a first computer-readable medium; and    a computer program executed by the processor from the first computer-readable medium to provide for hierarchical semiconductor structure design utilizing a basic atom, wherein the program provides for a hierarchy of abstractions ordered from highest to lowest, wherein the lowest abstraction corresponds to the basic atom, wherein the highest abstraction corresponds to the structure, wherein each abstraction relates a plurality of instances of an immediately lower abstraction, and wherein each instance of an abstraction has a set of parameters such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction    
   
   
       12 . The computer of  claim 11 , wherein the semiconductor structure design comprises a semiconductor test structure design.  
   
   
       13 . The computer of  claim 11 , wherein a set of parameters contains information relating to physical characteristics of the instance of an abstraction, wherein the physical characteristics are from a group consisting of: 
 grid placement information relating to the overall grid requirements of the semiconductor fabrication technology;    physical location of the instance of the abstraction, with respect to the overall grid requirement;    physical location of the instance of the abstraction, with respect to other instances of the abstraction;    electrical characteristics of the instance of the abstraction;    electrical characteristic limitation of required by the semiconductor fabrication technology;    power consumption of the instances of the abstraction;    density of the instances of the abstraction;    physical size of the instances of the abstraction;    connectivity information of the instance of the abstraction with respect to other instances of abstractions; and    requirements specific to a particular instance of the abstraction.    
   
   
       14 . The computer of  claim 11 , wherein the semiconductor structure design comprises a semiconductor chip structure design.  
   
   
       15 . The computer of  claim 11 , comprising: 
 a second computer-readable medium;    wherein the second computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.    
   
   
       16 . An article comprising a computer readable medium having a computer program stored thereon for execution on a computer with instructions to utilize a basic atom cell in design of a semiconductor structure, the program article comprising: 
 representing a hierarchical semiconductor structure design utilizing a basic atom;    providing for a hierarchy of abstractions ordered from highest to lowest, wherein the lowest abstraction corresponds to the basic atom, wherein the highest abstraction corresponds to the semiconductor structure, wherein each abstraction relates a plurality of instances of an immediately lower abstraction, and wherein each instance of an abstraction has a set of parameters such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.    
   
   
       17 . The article of  claim 16 , wherein the hierarchy of abstractions ordered from lowest to the highest comprises: atoms, higher order cells, devices, structures, circuits and integrated circuit chips.  
   
   
       18 . An article comprising a computer readable medium having a computer program stored thereon for execution on a computer with instructions to utilize a basic atom cell in design of a semiconductor structure, the program article comprising representing a hierarchical semiconductor structure design utilizing a basic atom.  
   
   
       19 . The article of  claim 18 , wherein the program article comprises: 
 providing for a hierarchy of abstractions ordered from highest to lowest, wherein the lowest abstraction corresponds to the basic atom, and the highest abstraction corresponds to the semiconductor structure.    
   
   
       20 . The article of  claim 19 , wherein the program article comprises: 
 each abstraction relates a plurality of instances of an immediately lower abstraction.    
   
   
       21 . The article of  claim 20 , wherein the program article comprises: 
 wherein each instance of an abstraction has a set of parameters such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.    
   
   
       22 . The article of  claim 20 , wherein the program article comprises: 
 where any abstraction of a higher abstraction other than the atom cell is defined by instantiations of immediately lower abstractions.    
   
   
       23 . A computer, comprising: 
 a first computer-readable medium;    a processor;    a computer program executed by the processor from the first computer-readable medium to provide for a hierarchy based semiconductor structure;    wherein the hierarchical structure includes a plurality of semiconductor structure components, each with associated parameters and hierarchy levels;    wherein a component with a higher hierarchy level is created by instantiating components with hierarchy levels; and    wherein a modification to a parameter value of a component of a higher level of hierarchy results in automatic modification of one or more parameter values of a lower level of hierarchy.    
   
   
       24 . The computer of  claim 23 , comprising the semiconductor structure comprises a semiconductor chip structure design.  
   
   
       25 . The computer of  claim 23 , comprising a second computer-readable medium, wherein the second computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.  
   
   
       26 . A computer, comprising: 
 a first computer-readable medium;    a processor; and    a computer program executed by the processor from the first computer-readable medium to provide for a hierarchy based semiconductor structure.    
   
   
       27 . The computer of  claim 26 , wherein the hierarchical structure includes a plurality of semiconductor structure components, each with associated parameters and hierarchy levels.  
   
   
       28 . The computer of  claim 27 , wherein a component with a higher hierarchy level is created by instantiating components with lower hierarchy levels.  
   
   
       29 . The computer of  claim 28 , wherein a modification to a parameter value of a component of a higher hierarchy level results in automatic modification of one or more parameter values of a lower hierarchy level.  
   
   
       30 . The computer of  claim 26 , wherein the semiconductor structure comprises a semiconductor chip structure design.  
   
   
       31 . The computer of  claim 26 , comprising a second computer-readable medium, wherein the second computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.  
   
   
       32 . A computer, comprising: 
 a processor;    a first computer-readable medium;    a hierarchical structure designator computer program executed by the processor from the first computer-readable medium to provide for hierarchical semiconductor structure design utilizing a basic atom; and    a component design computer program executed by the processor from the first computer-readable medium, capable of communicating with the hierarchical structure computer program, that permits a designer to place and modify characteristics of various electronic representations of components of a semiconductor structure.    
   
   
       33 . The computer of  claim 32 , wherein the semiconductor structure design comprises a semiconductor test structure design.  
   
   
       34 . The computer of  claim 32 , wherein the semiconductor structure design comprises a semiconductor chip structure design.  
   
   
       35 . The computer of  claim 32 , wherein the hierarchical structure computer program orders components hierarchy level from highest to lowest, wherein the lowest abstraction corresponds to the basic atom.  
   
   
       36 . The computer of  claim 35 , wherein each instance of a component relates a one or more instances of components with a lower hierarchy level.  
   
   
       37 . The computer of  claim 36 , wherein each instance of a component has a set of parameters; and 
 wherein modification of an instance of a component of a higher hierarchy level changes at least one parameter of instances of components related by the component of a higher hierarchy level.    
   
   
       38 . The computer of  claim 32 , comprising a second computer-readable medium, wherein the second computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.  
   
   
       39 . A computer comprising: 
 a processor;    a first computer-readable medium;    a hierarchical structure designator computer program executed by the processor from the first computer-readable medium to provide for hierarchical semiconductor structure design utilizing a basic atom;    a component design computer program executed by the processor from the first computer-readable medium, capable of communicating with the hierarchical structure computer program, that permits a designer to place and modify characteristics of various electronic representations of components of a semiconductor structure;    wherein the semiconductor structure design comprises a semiconductor test structure design;    wherein the semiconductor structure design comprises a semiconductor chip structure design;    wherein the hierarchical structure computer program orders components hierarchy level from highest to lowest, wherein the lowest abstraction corresponding to the basic atom;    wherein each instance of a component relates a one or more instances of components with a lower hierarchy level; and    wherein modification of an instance of a component of a higher hierarchy level changes at least one parameter of instances of components related by the component of a higher hierarchy.    
   
   
       40 . The computer of  claim 39 , wherein the component design computer program is Design Framework II software available from Cadence Design Systems, Inc.  
   
   
       41 . The computer of  claim 39 , comprising: 
 data that describes the hierarchical semiconductor structure design;    a second computer-readable medium;    wherein the second computer-readable medium stores data that describes the hierarchical semiconductor structure design, including parameter data of instances of abstractions.    
   
   
       42 . A computer comprising: 
 a processor;    a computer-readable medium; and,    a computer program executed by the processor from the medium to provide for designation of semiconductor design structure components by levels of hierarchy;    wherein the computer program:    creates one or more basic atom cells having at least one parameter that affects at least one attribute of the basic atom cell; and    creates at least one cell of a higher level of hierarchy than the one or more    basic atomic cells, that instantiates one or more basic atom cells; and    wherein changing one or more parameters of cells of higher level of hierarchy automatically changes associated parameters of the one or more basic atom cells instantiated by the cell of higher level of hierarchy.    
   
   
       43 . The computer of  claim 42 , wherein the semiconductor structure comprises a semiconductor test structure.  
   
   
       44 . The computer of  claim 42 , wherein the semiconductor structure comprises a semiconductor chip structure.  
   
   
       45 . The computer of  claim 42 , further comprising: 
 creating at least one device, each device relating a plurality of instances of cells;    wherein changing one or more parameters of an instance of a device automatically changes associated parameters of a plurality of instances of cells related by the device.    
   
   
       46 . The computer of  claim 45 , further comprising: 
 creating a structure, each structure relating a plurality of instances of devices, wherein changing one or more parameters of an instances of a structure automatically changes associated parameters of a plurality of instances of devices related by the structure.