Inventor · disambiguated record
John M. Maclaren
Also filed as: MACLAREN JOHN · MACLAREN JOHN M · MACLAREN JOHN MICHAEL
52 granted patents·2 pending applications·2,164 citations·filing 1996–2021
99Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO23CADENCE DESIGN SYSTEMS INC15COMPAQ COMPUTER CORP7COMPAQ INFORMATION TECHNOLOGIE2ESPINOZA ANNE1
Top patents by PatentIndex Score
54 records- 0198US6715116B2Memory data verify operationHEWLETT PACKARD COMPANY L P·Filed 2001·Granted Mar 30, 2004·228 cites·65 claims
- 0297US7010652B2Method for supporting multi-level striping of non-homogeneous memory to maximize concurrencyHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Mar 7, 2006·136 cites·12 claims
- 0397US6785785B2Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrencyHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 31, 2004·140 cites·16 claims
- 0496US7194577B2Memory latency and bandwidth optimizationsHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 20, 2007·128 cites·17 claims
- 0596US6938133B2Memory latency and bandwidth optimizationsHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 30, 2005·144 cites·19 claims
- 0695US10642538B1Multi-channel memory interfaceCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted May 5, 2020·19 cites·17 claims
- 0795US10282250B1Apparatus and method for a coherent, efficient, and configurable cyclic redundancy check retry implementation for synchronous dynamic random access memoryCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 7, 2019·22 cites·20 claims
- 0895US6845472B2Memory sub-system error cleansingHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jan 18, 2005·105 cites·85 claims
- 0995US6766469B2Hot-replace of memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jul 20, 2004·139 cites·63 claims
- 1094US7320086B2Error indication in a raid memory systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Jan 15, 2008·41 cites·18 claims
- 1193US10303543B1System and method for memory control having address integrity protection for error-protected data words of memory transactionsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 28, 2019·14 cites·20 claims
- 1293US10275306B1System and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurationsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Apr 30, 2019·14 cites·20 claims
- 1393US6832340B2Real-time hardware memory scrubbingHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Dec 14, 2004·90 cites·40 claims
- 1492US10769013B1Caching error checking data for memory having inline storage configurationsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 8, 2020·17 cites·20 claims
- 1592US6651138B2Hot-plug memory catridge power control logicHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Nov 18, 2003·98 cites·49 claims
- 1691US6854070B2Hot-upgrade/hot-add memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Feb 8, 2005·75 cites·56 claims
- 1790US6785835B2Raid memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 31, 2004·47 cites·36 claims
- 1889US10037246B1System and method for memory control having self writeback of data stored in memory with correctable errorCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jul 31, 2018·14 cites·15 claims
- 1988US10719058B1System and method for memory control having selectively distributed power-on processingCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jul 21, 2020·11 cites·15 claims
- 2087US10579470B1Address failure detection for memory devices having inline storage configurationsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 3, 2020·6 cites·20 claims
- 2187US10446215B1System and method for adaptively optimized refresh of memoryCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 15, 2019·11 cites·20 claims
- 2286US6711703B2Hard/soft error detectionHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Mar 23, 2004·39 cites·25 claims
- 2385US10642684B1Memory command interleavingCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted May 5, 2020·5 cites·20 claims
- 2484US10956342B1Variable channel multi-controller memory systemCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Mar 23, 2021·5 cites·19 claims
- 2584US10534565B1Programmable, area-optimized bank group rotation system for memory devicesCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jan 14, 2020·7 cites·20 claims
- 2684US7028213B2Error indication in a raid memory systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Apr 11, 2006·36 cites·33 claims
- 2782US6517375B2Technique for identifying multiple circuit componentsCOMPAQ INFORMATION TECHNOLOGIE·Filed 2001·Granted Feb 11, 2003·22 cites·15 claims
- 2881US5930496AComputer expansion slot and associated logic for automatically detecting compatibility with an expansion cardCOMPAQ COMPUTER CORP·Filed 1997·Granted Jul 27, 1999·116 cites·37 claims
- 2979US6640282B2Hot replace power control sequence logicHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Oct 28, 2003·25 cites·23 claims
- 3078US6608564B2Removable memory cartridge system for use with a server or other processor-based deviceHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 19, 2003·18 cites·23 claims
- 3177US6321286B1Fault tolerant computer systemCOMPAQ COMPUTER CORP·Filed 2000·Granted Nov 20, 2001·18 cites·15 claims
- 3274US7116241B2Removable memory cartridge system for use with a server or other processor-based deviceHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Oct 3, 2006·13 cites·34 claims
- 3372US6832286B2Memory auto-prechargeHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Dec 14, 2004·17 cites·28 claims
- 3472US6098137AFault tolerant computer systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 1, 2000·47 cites·12 claims
- 3570US6981095B1Hot replace power control sequence logicHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Dec 27, 2005·12 cites·32 claims
- 3668US6747563B2Removable memory cartridge system for use with a server or other processor-based deviceHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jun 8, 2004·9 cites·26 claims
- 3767US6692293B2Technique for identifying multiple circuit componentsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Feb 17, 2004·9 cites·29 claims
- 3867US6487621B1Architecture, system and method for ensuring an ordered transaction on at least one of a plurality of multi-processor buses that experience a hit-to-modified snoop cycleCOMPAQ INFORMATION TECHNOLOGIE·Filed 1999·Granted Nov 26, 2002·46 cites·19 claims
- 3965US6975241B2Removable memory cartridge system for use with a server or other processor-based deviceHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Dec 13, 2005·7 cites·35 claims
- 4065US5872941AProviding data from a bridge to a requesting device while the bridge is receiving the dataCOMPAQ COMPUTER CORP·Filed 1996·Granted Feb 16, 1999·46 cites·33 claims
- 4164US6052513AMulti-threaded bus masterCOMPAQ COMPUTER CORP·Filed 1996·Granted Apr 18, 2000·42 cites·49 claims
- 4263US6108741AOrdering transactionsFiled 1996·Granted Aug 22, 2000·41 cites·49 claims
- 4362US11720287B1System and method for memory managementCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Aug 8, 2023·0 cites·20 claims
- 4461US8098535B2Method and apparatus for gate training in memory interfacesMACLAREN JOHN·Filed 2009·Granted Jan 17, 2012·6 cites·20 claims
- 4561US7044770B2Technique for identifying multiple circuit componentsHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted May 16, 2006·6 cites·29 claims
- 4658US6055590ABridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer sizeCOMPAQ COMPUTER CORP·Filed 1996·Granted Apr 25, 2000·34 cites·23 claims
- 4756US11663149B1System and method for memory managementCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted May 30, 2023·0 cites·20 claims
- 4850US6075929APrefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transactionCOMPAQ COMPUTER CORP·Filed 1996·Granted Jun 13, 2000·22 cites·36 claims
- 4946US7952945B2Method and apparatus for determining write leveling delay for memory interfacesCADENCE DESIGN SYSTEMS INC·Filed 2009·Granted May 31, 2011·1 cites·20 claims
- 5045US7353328B2Memory testingHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Apr 1, 2008·4 cites·17 claims
Showing the top 50 of 54 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →