Inventor · disambiguated record
John C. Pescatore
Also filed as: PESCATORE JOHN ANTHONY · PESCATORE JOHN C · PESCATORE JOHN CARMINE · PESCATORE JR JOHN C
13 granted patents·2 pending applications·722 citations·filing 1984–2009
94Inventor score
Top patents by PatentIndex Score
15 records- 0191US4870566AScannerless message concentrator and communications multiplexerIBM·Filed 1984·Granted Sep 26, 1989·115 cites·12 claims
- 0291US4837677AMultiple port service expansion adapter for a communications controllerIBM·Filed 1985·Granted Jun 6, 1989·171 cites·8 claims
- 0386US4716523AMultiple port integrated DMA and interrupt controller and arbitratorIBM·Filed 1985·Granted Dec 29, 1987·109 cites·17 claims
- 0486US4648029AMultiplexed interrupt/DMA request arbitration apparatus and methodIBM·Filed 1984·Granted Mar 3, 1987·86 cites·7 claims
- 0582US7415551B2Multi-host virtual bridge input-output resource switchDELL PRODUCTS LP·Filed 2003·Granted Aug 19, 2008·36 cites·15 claims
- 0679US4751634AMultiple port communications adapter apparatusIBM·Filed 1985·Granted Jun 14, 1988·71 cites·5 claims
- 0765US8341499B2System and method for error detection in a redundant memory systemPESCATORE JOHN C·Filed 2009·Granted Dec 25, 2012·3 cites·9 claims
- 0865US6321296B1SDRAM L3 cache using speculative loads with command aborts to lower latencyIBM·Filed 1998·Granted Nov 20, 2001·46 cites·17 claims
- 0962US4627054AMultiprocessor array error detection and recovery apparatusIBM·Filed 1984·Granted Dec 2, 1986·28 cites·5 claims
- 1055US8321758B2Data error correction device and methods thereofPESCATORE JOHN C·Filed 2008·Granted Nov 27, 2012·3 cites·20 claims
- 1147US2006077750A1System and method for error detection in a redundant memory systemDELL PRODUCTS LP·Filed 2004·Application pending·0 cites
- 1246US5809537AMethod and system for simultaneous processing of snoop and cache operationsIBM·Filed 1997·Granted Sep 15, 1998·20 cites·12 claims
- 1346US5754865ALogical address bus architecture for multiple processor systemsIBM·Filed 1995·Granted May 19, 1998·19 cites·12 claims
- 1445US2004064065A1Individual illusion systemFiled 2003·Application pending·0 cites
- 1542US5604754AValidating the synchronization of lock step operated circuitsIBM·Filed 1995·Granted Feb 18, 1997·15 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →