System and method for error detection in a redundant memory system

Abstract

A system and method is disclosed for detecting errors in memory. A memory subsystem that includes a set of parallel memory channels is disclosed. Data is saved such that a duplicate copy of data is saved to the opposite memory channel according to a horizontal mirroring scheme or a vertical mirroring scheme. A cyclic redundancy code is generated on the basis of the data bits and address bits. The generated cyclic redundancy code and a copy of the cyclic redundancy code are saved to the memory channels according to a horizontal mirroring scheme or a vertical mirroring scheme.

1 . A method for identifying errors in the memory of a computer system, comprising: 
 generating a set of cyclic redundancy code bits from a set of data bits and associated address bits;    saving the data bits and the cyclic redundancy code bits to a first memory location;    saving a duplicate of the data bits and the cyclic redundancy code bits to a second memory location;    retrieving the data bits and the cyclic redundancy code bits from the first memory location;    generating a second set of cyclic redundancy code bits on the basis of the retrieved data bits and associated address bits; and    comparing the retrieved cyclic redundancy code bits with the second set of the cyclic redundancy code bits.    
   
   
       2 . The method for identifying errors in the memory of a computer system of  claim 1 , further comprising the step of retrieving the duplicate of the data bits and the cyclic redundancy code bits if the retrieved cyclic redundancy code bits are not identical to the second set of the cyclic redundancy code bits.  
   
   
       3 . The method for identifying errors in the memory of a computer system of  claim 1 , wherein the step of generating a set of cyclic redundancy code bits from a set of data bits and associated address bits comprises the step of generating a set of cyclic redundancy code bits in a logic element of a memory controller.  
   
   
       4 . The method for identifying errors in the memory of a computer system of  claim 1 , wherein the step of saving the data bits and the cyclic redundancy code bits to a first memory location comprises the step of saving the data bits and cyclic redundancy code bits to a first memory location associated with a first memory channel; and 
 wherein the step of saving a duplicate of the data bits and the cyclic redundancy code bits to a second memory location comprises the step of saving the duplicate of the data bits and cyclic redundancy code bits to a second memory location associated with a second memory channel.    
   
   
       5 . The method for identifying errors in the memory of a computer system of  claim 4 , wherein the first memory location and the second memory location are dual in-line memory modules.  
   
   
       6 . The method for identifying errors in the memory of a computer system of  claim 5 , wherein the cyclic redundancy code bits are saved across multiple memory rows in the first memory location and wherein the duplicate of the cyclic redundancy code bits are saved across multiple memory rows in the second memory location.  
   
   
       7 . The method for identifying errors in the memory of a computer system of  claim 2 , wherein the step of retrieving the duplicate of the data bits and the cyclic redundancy code bits is followed by the steps of: 
 generating a third set of cyclic redundancy code bits on the basis of the retrieved duplicate data bits and associated address bits; and    comparing the retrieved cyclic redundancy code bits with the third set of the cyclic redundancy code bits.    
   
   
       8 . A method for identifying errors in the memory of a computer system, comprising: 
 generating a set of cyclic redundancy code bits from a set of data bits and respective address bits;    saving a first portion of the data bits and the cyclic redundancy bits to a first memory location;    saving a duplicate of the first portion of the data bits and the cyclic redundancy bits to a second memory location;    saving a second portion of the data bits and the cyclic redundancy bits to a second memory location;    saving a duplicate of the second portion of the data bits and the cyclic redundancy bits to a first memory location    retrieving the first portion of the data bits and the cyclic redundancy code bits from the first memory location and the second portion of the data bits and the cyclic redundancy code bits from the second memory location;    generating a second set of cyclic redundancy code bits on the basis of the retrieved data bits; and    comparing the retrieved cyclic redundancy code bits with the second set of the cyclic redundancy code bits.    
   
   
       9 . The method for identifying errors in the memory of a computer system of  claim 8 , further comprising the step of retrieving the duplicate of the first portion of the data bits and the cyclic redundancy code bits and the duplicate of the second portion of the data bits and the cyclic redundancy code bits if the retrieved cyclic redundancy code bits are not identical to the second set of the cyclic redundancy code bits.  
   
   
       10 . The method for identifying errors in the memory of a computer system of  claim 9 , wherein the step of generating a set of cyclic redundancy code bits from a set of data bits comprises the step of generating a set of cyclic redundancy code bits in a logic element of a memory controller.  
   
   
       11 . The method for identifying errors in the memory of a computer system of  claim 10 , wherein the step of generating a second set of cyclic redundancy code bits on the basis of the retrieved data bits comprises the step of generating a second set of cyclic redundancy code bits in the logic element of the memory controller.  
   
   
       12 . The method for identifying errors in the memory of a computer system of  claim 8 , wherein the data bits are divided into four sets; 
 wherein the first and third sets comprise the first portion of the data bits saved to a first memory location;    wherein the second and fourth sets comprise the second portion of the data bits saved to a second memory location.    
   
   
       13 . The method for identifying errors in the memory of a computer system of  claim 8 , 
 wherein the duplicate data bits are divided into four sets;    wherein the first and third sets comprise the first portion of the data bits saved to a second memory location;    wherein the second and fourth sets comprise the second portion of the data bits saved to a first memory location.    
   
   
       14 . The method for identifying errors in the memory of a computer system of  claim 8 , 
 wherein the first memory location is accessible through a first memory channel;    wherein the second memory location is accessible through a second memory channel; and    wherein the first memory channel is logically parallel to the second memory channel.    
   
   
       15 . The method for identifying errors in the memory of a computer system of  claim 14 , wherein the first memory location and the second memory location are dual in-line memory modules.  
   
   
       16 . The method for identifying errors in the memory of a computer system of  claim 9 , wherein the step of retrieving the duplicate of the data bits and the cyclic redundancy code bits is followed by the steps of: 
 generating a third set of cyclic redundancy code bits on the basis of the retrieved duplicate data bits; and    comparing the retrieved cyclic redundancy code bits with the third set of the cyclic redundancy code bits.    
   
   
       17 . A memory subsystem, comprising: 
 a memory controller;    a first memory channel coupled to the memory controller, the first memory channel comprising a plurality of memory lines for storing a code word comprising a set of data bits and a cyclic redundancy code generated on the basis of the set of data bits and corresponding address bits; and    a second memory channel couple to the memory controller, the second memory channel comprising a plurality of memory lines for storing a duplicate of the data bits and cyclic redundancy code of the first memory channel.    
   
   
       18 . The memory subsystem of  claim 17 , wherein the memory controller includes a logic element for generating a cyclic redundancy code on the basis of a set of data bits.  
   
   
       19 . A memory subsystem, comprising: 
 a memory controller;    a first memory channel coupled to the memory controller, the first memory channel comprising a plurality of memory lines for storing a first portion of a code word, a first portion of a cyclic redundancy code generated on the basis of the code word, a duplicate of the second portion of the code word, and a duplicate of the second portion of a cyclic redundancy code generated on the basis of the code word; and    a second memory channel coupled to the memory controller, the second memory channel comprising a plurality of memory lines for storing a duplicate of the first portion of a code word, a duplicate of the first portion of a cyclic redundancy code generated on the basis of the code word, a second portion of the code word, and a second portion of a cyclic redundancy code generated on the basis of the code word.    
   
   
       20 . The memory subsystem of  claim 19 , wherein the memory controller includes a logic element for generating a cyclic redundancy code on the basis of a set of data bits.