Inventor · disambiguated record
John W. Ward, Iii
Also filed as: WARD III JOHN W · WARD III JOHN WESLEY · WARD JOHN WESLEY
18 granted patents·2 pending applications·276 citations·filing 2003–2013
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0196US7487334B2Branch encoding before instruction cache writeIBM·Filed 2005·Granted Feb 3, 2009·61 cites·1 claims
- 0296US7269715B2Instruction grouping history on fetch-side dispatch group formationIBM·Filed 2005·Granted Sep 11, 2007·62 cites·14 claims
- 0385US7827388B2Apparatus for adjusting instruction thread priority in a multi-thread processorIBM·Filed 2008·Granted Nov 2, 2010·13 cites·13 claims
- 0481US8661230B2Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executionsALEXANDER GREGORY W·Filed 2011·Granted Feb 25, 2014·5 cites·7 claims
- 0579US9069546B2Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executionsALEXANDER GREGORY W·Filed 2012·Granted Jun 30, 2015·4 cites·7 claims
- 0679US7769984B2Dual-issuance of microprocessor instructions using dual dependency matricesIBM·Filed 2008·Granted Aug 3, 2010·9 cites·1 claims
- 0778US7401208B2Method and apparatus for randomizing instruction thread interleaving in a multi-thread processorIBM·Filed 2003·Granted Jul 15, 2008·23 cites·11 claims
- 0878US7013400B2Method for managing power in a simultaneous multithread processor by loading instructions into pipeline circuit during select times based on clock signal frequency and selected power modeIBM·Filed 2003·Granted Mar 14, 2006·27 cites·20 claims
- 0976US7360062B2Method and apparatus for selecting an instruction thread for processing in a multi-thread processorIBM·Filed 2003·Granted Apr 15, 2008·21 cites·10 claims
- 1069US7549095B1Error detection enhancement in a microprocessor through the use of a second dependency matrixIBM·Filed 2008·Granted Jun 16, 2009·4 cites·1 claims
- 1169US7469407B2Method for resource balancing using dispatch flush in a simultaneous multithread processorIBM·Filed 2003·Granted Dec 23, 2008·13 cites·5 claims
- 1269US7401207B2Apparatus and method for adjusting instruction thread priority in a multi-thread processorIBM·Filed 2003·Granted Jul 15, 2008·13 cites·6 claims
- 1366US7213135B2Method using a dispatch flush in a simultaneous multithread processor to resolve exception conditionsIBM·Filed 2003·Granted May 1, 2007·11 cites·15 claims
- 1463US7822954B2Methods, systems, and computer program products for recovering from branch prediction latencyIBM·Filed 2008·Granted Oct 26, 2010·2 cites·24 claims
- 1560US7305586B2Accessing and manipulating microprocessor stateIBM·Filed 2003·Granted Dec 4, 2007·7 cites·15 claims
- 1657US8145885B2Apparatus for randomizing instruction thread interleaving in a multi-thread processorKALLA RONALD NICK·Filed 2008·Granted Mar 27, 2012·1 cites·6 claims
- 1756US9342307B2Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executionsIBM·Filed 2013·Granted May 17, 2016·0 cites·15 claims
- 1849US2008162904A1Apparatus for selecting an instruction thread for processing in a multi-thread processorKALLA RONALD NICK·Filed 2008·Application pending·0 cites
- 1947US2009217017A1Method, system and computer program product for minimizing branch prediction latencyIBM·Filed 2008·Application pending·0 cites
- 2046US7475223B2Fetch-side instruction dispatch group formationIBM·Filed 2005·Granted Jan 6, 2009·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →