Apparatus for selecting an instruction thread for processing in a multi-thread processor

Abstract

The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement component produces at least one base instruction thread selection signal that indicates a particular one of the instruction threads for passing an instruction from that particular thread into a stream of interleaved instructions. Thread selection modification is provided by an interleave modification component that generates a final thread selection signal based upon the base thread selection signal and a feedback signal derived from one or more conditions or events in the various processor elements. This final thread selection signal may indicate the same instruction thread indicated by the base thread selection signal or a different one of the instruction threads for passing an instruction into the interleaved stream of instructions.

1 . A circuit for controlling cycle-by-cycle interleaving of instructions between a number of instruction threads in a simultaneous multithreading processor, the circuit including:
 (a) a first selection input connected to receive a base thread selection signal based at least in part on an interleaving rule which specifies a relative frequency at which instructions are to be taken from each of the number of instruction threads, the base thread selection signal indicating a first instruction thread from among the number of instruction threads;   (b) an additional selection input connected to receive an additional base thread selection signal indicating a second instruction thread from among the number of instruction threads;   (c) a feedback input connected to receive a processor element feedback signal associated with one of the instruction threads included in the number of instruction threads;   (d) a modification component for generating a final thread selection signal based upon the base thread selection signal received at the first selection input and the feedback signal received at the feedback input, and for generating an additional final thread selection signal based upon the additional thread selection signal received at the additional selection input and an additional feedback signal received at an additional feedback input;   (e) an output component for combining the final thread selection signal and the additional final thread selection signal to produce a thread selection control signal to effect a selection of one of the number of instruction threads for the purpose of interleaving an instruction into an interleaved stream of instructions.   
   
   
       2 . The circuit of  claim 1  further including:
 (a) a first thread hold element for selectively holding the first instruction thread based on a state of the final thread selection signal; and   (b) an additional thread hold element for selectively holding the second instruction thread based on a state of the additional final thread selection signal.   
   
   
       3 . The circuit of  claim 1  further including a first feedback override circuit for overriding the processor element feedback signal when the number of instruction threads have different processing priorities. 
   
   
       4 . The circuit of  claim 3  further including an additional feedback override circuit for overriding the additional feedback signal when the number of instruction threads have different processing priorities.