Inventor · disambiguated record
John-David Wellman
Also filed as: WELLMAN JOHN D · WELLMAN JOHN-DAVID
33 granted patents·11 pending applications·510 citations·filing 2000–2023
97Inventor score
Top patents by PatentIndex Score
44 records- 0195US7793081B2Implementing instruction set architectures with non-contiguous register file specifiersIBM·Filed 2008·Granted Sep 7, 2010·34 cites·5 claims
- 0295US7496733B2System and method of execution of register pointer instructions ahead of instruction issuesIBM·Filed 2007·Granted Feb 24, 2009·38 cites·20 claims
- 0395US7421566B2Implementing instruction set architectures with non-contiguous register file specifiersIBM·Filed 2006·Granted Sep 2, 2008·38 cites·1 claims
- 0494US8166281B2Implementing instruction set architectures with non-contiguous register file specifiersGSCHWIND MICHAEL KARL·Filed 2009·Granted Apr 24, 2012·30 cites·16 claims
- 0594US6779049B2Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanismIBM·Filed 2000·Granted Aug 17, 2004·74 cites·14 claims
- 0694US6678795B1Method and apparatus for memory prefetching based on intra-page usage historyIBM·Filed 2000·Granted Jan 13, 2004·105 cites·34 claims
- 0793US8918623B2Implementing instruction set architectures with non-contiguous register file specifiersGSCHWIND MICHAEL KARL·Filed 2012·Granted Dec 23, 2014·23 cites·18 claims
- 0891US11740933B2Heterogeneous system on a chip scheduler with learning agentIBM·Filed 2020·Granted Aug 29, 2023·3 cites·20 claims
- 0987US8893095B2Methods for generating code for an architecture encoding an extended register specificationGSCHWIND MICHAEL KARL·Filed 2012·Granted Nov 18, 2014·7 cites·12 claims
- 1086US8589662B2Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signalsALTMAN ERIK R·Filed 2012·Granted Nov 19, 2013·10 cites·20 claims
- 1184US6711651B1Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetchingIBM·Filed 2000·Granted Mar 23, 2004·39 cites·22 claims
- 1282US11966776B2Learning agent based application schedulingIBM·Filed 2021·Granted Apr 23, 2024·1 cites·20 claims
- 1381US9619385B2Single thread cache miss rate estimationIBM·Filed 2015·Granted Apr 11, 2017·3 cites·13 claims
- 1479US8151092B2Control signal memoization in a multiple instruction issue microprocessorALTMAN ERIK RICHTER·Filed 2005·Granted Apr 3, 2012·10 cites·6 claims
- 1578US6970982B2Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructionsIBM·Filed 2003·Granted Nov 29, 2005·20 cites·12 claims
- 1677US11704155B2Heterogeneous system on a chip schedulerIBM·Filed 2020·Granted Jul 18, 2023·1 cites·20 claims
- 1776US7509457B2Non-homogeneous multi-processor system with shared memoryIBM·Filed 2005·Granted Mar 24, 2009·4 cites·1 claims
- 1875US8091050B2Modeling system-level effects of soft errorsBOSE PRADIP·Filed 2008·Granted Jan 3, 2012·7 cites·20 claims
- 1974US8312424B2Methods for generating code for an architecture encoding an extended register specificationGSCHWIND MICHAEL KARL·Filed 2008·Granted Nov 13, 2012·4 cites·11 claims
- 2074US7461209B2Transient cache storage with discard function for disposable dataIBM·Filed 2005·Granted Dec 2, 2008·6 cites·15 claims
- 2172US6820142B2Token based DMAIBM·Filed 2000·Granted Nov 16, 2004·17 cites·20 claims
- 2270US6907477B2Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processorsIBM·Filed 2004·Granted Jun 14, 2005·11 cites·11 claims
- 2368US8893079B2Methods for generating code for an architecture encoding an extended register specificationGSCHWIND MICHAEL KARL·Filed 2012·Granted Nov 18, 2014·1 cites·9 claims
- 2464US7865699B2Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing codeIBM·Filed 2007·Granted Jan 4, 2011·2 cites·25 claims
- 2562US7454597B2Computer processing system employing an instruction schedule cacheIBM·Filed 2007·Granted Nov 18, 2008·2 cites·10 claims
- 2661US8000953B2Augmenting of automated clustering-based trace sampling methods by user-directed phase detectionIBM·Filed 2007·Granted Aug 16, 2011·3 cites·17 claims
- 2759US7340588B2Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing codeIBM·Filed 2003·Granted Mar 4, 2008·5 cites·39 claims
- 2857US7325124B2System and method of execution of register pointer instructions ahead of instruction issueIBM·Filed 2004·Granted Jan 29, 2008·4 cites·21 claims
- 2956US7130963B2System and method for instruction memory storage and processing based on backwards branch control informationIBM·Filed 2003·Granted Oct 31, 2006·5 cites·21 claims
- 3054US7206923B2Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-fillingIBM·Filed 2003·Granted Apr 17, 2007·3 cites·22 claims
- 3153US11360772B2Instruction sequence merging and splitting for optimized accelerator implementationIBM·Filed 2020·Granted Jun 14, 2022·0 cites·20 claims
- 3252US2017212786A1Dynamic tuning of a simultaneous multithreading metering architectureIBM·Filed 2016·Application pending·0 cites
- 3352US2024314151A1Detecting anomalous activity in a system-on-chipIBM·Filed 2023·Application pending·0 cites
- 3451US9626293B2Single-thread cache miss rate estimationIBM·Filed 2015·Granted Apr 18, 2017·0 cites·7 claims
- 3551US2007038984A1Methods for generating code for an architecture encoding an extended register specificationGSCHWIND MICHAEL K·Filed 2006·Application pending·0 cites
- 3650US2017212824A1Dynamic tuning of a simultaneous multithreading metering architectureIBM·Filed 2016·Application pending·0 cites
- 3748US8156310B2Method and apparatus for data stream alignment supportEICHENBERGER ALEXANDRE E·Filed 2006·Granted Apr 10, 2012·0 cites·20 claims
- 3846US2008263325A1System and structure for synchronized thread priority selection in a deeply pipelined multithreaded microprocessorIBM·Filed 2007·Application pending·0 cites
- 3945US2008168260A1Symbolic Execution of Instructions on In-Order ProcessorsZYUBAN VICTOR·Filed 2007·Application pending·0 cites
- 4044US2007162895A1Mechanism and method for two level adaptive trace predictionIBM·Filed 2006·Application pending·0 cites
- 4144US2008162877A1Non-Homogeneous Multi-Processor System With Shared MemoryALTMAN ERIK RICHTER·Filed 2008·Application pending·0 cites
- 4243US2006174089A1Method and apparatus for embedding wide instruction words in a fixed-length instruction set architectureIBM·Filed 2005·Application pending·0 cites
- 4343US2006236036A1Method and apparatus for predictive scheduling of memory accesses based on reference localityGSCHWIND MICHAEL K·Filed 2005·Application pending·0 cites
- 4443US2007050592A1Method and apparatus for accessing misaligned data streamsGSCHWIND MICHAEL K·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →