Methods for generating code for an architecture encoding an extended register specification

Abstract

There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

1 . A method for generating code for a fixed-width instruction set, comprising: 
 identifying a non-contiguous register specifier; and    generating a fixed-width instruction word that includes the non-contiguous register specifier.    
     
     
         2 . The method of  claim 1 , wherein the non-contiguous register specifier includes at least two sets of contiguous bits separated by at least one bit not part of the register specifier, and the method further comprises encoding a single logical register specifier into at least two non-contiguous fields of the non-contiguous register specifier.  
     
     
         3 . The method of  claim 2 , wherein the single logical register specifier is represented using a generic intrinsic that provides no indication of a partitioning of an operand specification into the non-contiguous register specifier.  
     
     
         4 . The method of  claim 1 , wherein a first set of bits in the non-contiguous register specifier is specified directly by an instruction field in the fixed-width instruction, and a second set of bits in the non-contiguous register specifier is specified directly by another instruction field in the fixed-width instruction.  
     
     
         5 . The method of  claim 1 , wherein a first set of bits in the non-contiguous register specifier is specified directly by an instruction field in the fixed-width instruction, a second set of bits in the non-contiguous register specifier is specified using a deep encoding, and the method further comprises generating a set of n bits for inclusion as part of the non-contiguous register specifier from a set of m bits encoded in the fixed-width instruction, wherein n is less than m, and the deep encoding involves allocating multiple opcode points or extended opcode points to indicate the fixed-width instruction, wherein each of the opcode points or the extended opcode points further indicates the use of a specific bit string as an extended register specifier.  
     
     
         6 . The method of  claim 1 , further comprising: 
 generating a first set of fixed-width instructions that allow referencing of a first set of registers with a contiguous register specifier; and    generating a second set of fixed-width instructions that allow referencing of a second set of registers using the non-contiguous register specifier, the second set of registers being larger than the first set of registers.    
     
     
         7 . The method of  claim 6 , wherein the second set of registers includes at least a subset of the first set of registers, the at least subset of the first set of registers being encoded by the second set of fixed-width instructions.  
     
     
         8 . The method of  claim 7 , further comprising generating the second set of fixed-width instructions using a compiling method for an extended register specification, the compiling method comprising allocating a first set of operands to the first set of registers, and allocating a second set of operands to the second set of registers, said allocating steps performed in accordance with an instruction set specification corresponding to the fixed-width instruction set.  
     
     
         9 . A method for compiling a program to use an extended register specification, comprising: 
 specifying a subset of physical registers using a first set of instructions, the subset of physical registers corresponding to a set of physical registers specified by a second set of instructions, the first set of instructions for encoding a set of semantics in accordance with an instruction set specification such that the set of semantics are capable of being encoded only by the first set of instructions; and    performing register coloring by allocating a respective symbolic register from a set of symbolic registers to a respective register class from a set of register classes based on an operation of an intermediate language that references the respective symbolic register as an operand, wherein the register coloring is performed for each of the symbolic registers in the set, the set of register classes are hierarchically arranged, and the set of symbolic registers are capable of being used with respect to the subset of physical registers, support encoding a subset of the set of semantics with the second set of instructions, and correspond to the extended register specification.    
     
     
         10 . The method of  claim 9 , wherein said step of performing register coloring further comprises: 
 generating an interference graph having nodes and edges, the nodes representing the set of symbolic registers, the edges connecting two of the nodes that are concurrently alive;    identifying each of the nodes representing a live range;    wherein the respective symbolic register, as represented by an identified node, is allocated to the respective register class by: 
 associating the identified node with the respective register class,  
 determining a least restrictive allowable class for the identified node from among any of the register classes in the set that are hierarchically included in the respective register class; and  
 associating a maximum allowable degree with each of the register classes in the set to enable coloring of each of the register classes in the set.  
   
     
     
         11 . The method of  claim 10 , wherein said step of performing register coloring further comprises: 
 determining whether a degree of the identified node is less than an allowable degree corresponding to the respective register class;    determining whether the degree of the identified node is less than the allowable degree relating to a particular register class that hierarchically includes the respective register class.    
     
     
         12 . The method of  claim 11 , wherein said step of performing register coloring further comprises pre-allocating any of the symbolic registers in the set corresponding to the respective register class.  
     
     
         13 . The method of  claim 9 , wherein said step of performing the register coloring test comprises generating an interference graph having nodes and edges, the nodes representing the set of symbolic registers, the edges connecting two of the nodes that are concurrently alive, and the method further comprises splitting a live range relating to at least one of the nodes into a first portion and a second portion, the first portion for allocation to a first register class, and the second portion for allocation to a hierarchically encompassing register class when the live range cannot be colored, the first register class and the hierarchically encompassing register class being included within the set of register classes, and first register class being included within the hierarchically encompassing register class.  
     
     
         14 . The method of  claim 9 , further comprising performing a spilling operation with respect to a hierarchically encompassing register class from the set when the respective symbolic register cannot be allocated to any of the register classes in the set that satisfy operand constraints for all operations referencing the respective symbolic register.  
     
     
         15 . The method of  claim 9 , further comprising the step of performing register coloring with respect to the subset of registers based on data derived from a program that includes generic intrinsics.  
     
     
         16 . A computer program product comprising a computer usable medium having computer usable program code for generating code for a fixed-width instruction set, said computer program product comprising: 
 computer usable program code for identifying a non-contiguous register specifier; and    computer usable program code for generating a fixed-width instruction word that includes the non-contiguous register specifier.    
     
     
         17 . The computer program product of  claim 16 , wherein the non-contiguous register specifier includes at least two sets of contiguous bits separated by at least one bit not part of the register specifier, and the computer program product further comprises computer usable program code for encoding a single logical register specifier into at least two non-contiguous fields of the non-contiguous register specifier.  
     
     
         18 . The computer program product of claim of  claim 17 , wherein the single logical register specifier is represented using a generic intrinsic that provides no indication of a partitioning of an operand specification into the non-contiguous register specifier.  
     
     
         19 . The computer program product of claim of  claim 16 , wherein a first set of bits in the non-contiguous register specifier is specified directly by an instruction field in the fixed-width instruction, and a second set of bits in the non-contiguous register specifier is specified directly by another instruction field in the fixed-width instruction.  
     
     
         20 . The computer program product of claim of  claim 16 , wherein a first set of bits in the non-contiguous register specifier is specified directly by an instruction field in the fixed-width instruction, a second set of bits in the non-contiguous register specifier is specified using a deep encoding, and the computer program product further comprises computer usable program code for generating a set of n bits for inclusion as part of the non-contiguous register specifier from a set of m bits encoded in the fixed-width instruction, wherein n is less than m, and the deep encoding involves allocating multiple opcode points or extended opcode points to indicate the fixed-width instruction, wherein each of the opcode points or the extended opcode points further indicates the use of a specific bit string as an extended register specifier.