Inventor · disambiguated record
Judge K. Arora
Also filed as: ARORA JUDGE K · ARORA JUDGE KEN · ARORA JUDGE KENNEDY
17 granted patents·2 pending applications·1,067 citations·filing 1995–2001
96Inventor score
Top patents by PatentIndex Score
19 records- 0193US5860017AProcessor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instructionINTEL CORP·Filed 1996·Granted Jan 12, 1999·182 cites·29 claims
- 0291US6272520B1Method for detecting thread switch eventsINTEL CORP·Filed 1997·Granted Aug 7, 2001·177 cites·12 claims
- 0381US6115808AMethod and apparatus for performing predicate hazard detectionINTEL CORP·Filed 1998·Granted Sep 5, 2000·99 cites·23 claims
- 0480US6065115AProcessor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instructionINTEL CORP·Filed 1998·Granted May 16, 2000·78 cites·31 claims
- 0577US6199144B1Method and apparatus for transferring data in a computer systemINTEL CORP·Filed 1997·Granted Mar 6, 2001·77 cites·20 claims
- 0676US6304955B1Method and apparatus for performing latency based hazard detectionINTEL CORP·Filed 1998·Granted Oct 16, 2001·75 cites·28 claims
- 0775US6304960B1Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditionsINTEL CORP·Filed 1998·Granted Oct 16, 2001·70 cites·25 claims
- 0872US6658559B1Method and apparatus for advancing load operationsINTEL CORP·Filed 1999·Granted Dec 2, 2003·62 cites·6 claims
- 0971US5948095AMethod and apparatus for prefetching data in a computer systemINTEL CORP·Filed 1997·Granted Sep 7, 1999·51 cites·6 claims
- 1064US6119218AMethod and apparatus for prefetching data in a computer systemINST THE DEV OF EMERGING ARCHI·Filed 1999·Granted Sep 12, 2000·37 cites·18 claims
- 1164US5832260AProcessor microarchitecture for efficient processing of instructions in a program including a conditional program flow control instructionINTEL CORP·Filed 1995·Granted Nov 3, 1998·44 cites·36 claims
- 1251US6219781B1Method and apparatus for performing register hazard detectionINTEL CORP·Filed 1998·Granted Apr 17, 2001·24 cites·26 claims
- 1351US2002054040A1System for graphical representation of real-time dataFiled 2001·Application pending·0 cites
- 1451US2002032637A1Method and apparatus for graphical representation of real-time dataFiled 2001·Application pending·0 cites
- 1549US6629238B1Predicate controlled software pipelined loop processing with prediction of predicate writing and value prediction for use in subsequent iterationINTEL CORP·Filed 1999·Granted Sep 30, 2003·21 cites·25 claims
- 1649US6393556B1Apparatus and method to change processor privilege without pipeline flushINTEL CORP·Filed 1998·Granted May 21, 2002·21 cites·18 claims
- 1748US6598156B1Mechanism for handling failing load check instructionsINTEL CORP·Filed 1999·Granted Jul 22, 2003·21 cites·28 claims
- 1844US6442678B1Method and apparatus for providing data to a processor pipelineINTEL CORP·Filed 1998·Granted Aug 27, 2002·16 cites·18 claims
- 1939US6401195B1Method and apparatus for replacing data in an operand latch of a pipeline stage in a processor during a stallINTEL CORP·Filed 1998·Granted Jun 4, 2002·12 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →