Inventor · disambiguated record
Juergen Koehl
Also filed as: KOEHL JUERGEN
38 granted patents·2 pending applications·447 citations·filing 1998–2015
97Inventor score
Top patents by PatentIndex Score
40 records- 0199US7308669B2Use of redundant routes to increase the yield and reliability of a VLSI layoutIBM·Filed 2005·Granted Dec 11, 2007·211 cites·40 claims
- 0287US6218631B1Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talkIBM·Filed 1998·Granted Apr 17, 2001·88 cites·9 claims
- 0380US7865855B2Method and system for generating a layout for an integrated electronic circuitIBM·Filed 2007·Granted Jan 4, 2011·10 cites·9 claims
- 0480US7386815B2Test yield estimate for semiconductor products created from a libraryIBM·Filed 2005·Granted Jun 10, 2008·9 cites·17 claims
- 0578US8234594B2Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the sameANDERSON BRENT A·Filed 2006·Granted Jul 31, 2012·7 cites·17 claims
- 0677US7145873B2Switching arrangement and method with separated output buffersIBM·Filed 2001·Granted Dec 5, 2006·25 cites·16 claims
- 0774US7526743B2Method for routing data paths in a semiconductor chip with a plurality of layersIBM·Filed 2005·Granted Apr 28, 2009·9 cites·25 claims
- 0871US7844931B2Method and computer system for optimizing the signal time behavior of an electronic circuit designIBM·Filed 2008·Granted Nov 30, 2010·6 cites·9 claims
- 0969US8015527B2Routing of wires of an electronic circuitIBM·Filed 2008·Granted Sep 6, 2011·5 cites·16 claims
- 1069US7962877B2Port assignment in hierarchical designs by abstracting macro logicIBM·Filed 2008·Granted Jun 14, 2011·4 cites·20 claims
- 1169US7392497B2Regular routing for deep sub-micron chip designIBM·Filed 2005·Granted Jun 24, 2008·7 cites·15 claims
- 1268US7996808B2Computer readable medium, system and associated method for designing integrated circuits with loop insertionsIBM·Filed 2008·Granted Aug 9, 2011·4 cites·8 claims
- 1368US7336115B2Redundancy in signal distribution treesIBM·Filed 2006·Granted Feb 26, 2008·3 cites·6 claims
- 1467US8762919B2Circuit macro placement using macro aspect ratio based on portsKEINERT JOACHIM·Filed 2010·Granted Jun 24, 2014·2 cites·18 claims
- 1567US7755408B2Redundancy in signal distribution treesIBM·Filed 2007·Granted Jul 13, 2010·4 cites·12 claims
- 1666US8972961B2Instruction scheduling approach to improve processor performanceKOEHL JUERGEN·Filed 2011·Granted Mar 3, 2015·2 cites·11 claims
- 1766US8935685B2Instruction scheduling approach to improve processor performanceKOEHL JUERGEN·Filed 2012·Granted Jan 13, 2015·2 cites·3 claims
- 1866US7886245B2Structure for optimizing the signal time behavior of an electronic circuit designIBM·Filed 2008·Granted Feb 8, 2011·4 cites·10 claims
- 1966US6904584B2Method and system for placing logic nodes based on an estimated wiring congestionIBM·Filed 2002·Granted Jun 7, 2005·14 cites·22 claims
- 2065US7984394B2Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the sameIBM·Filed 2007·Granted Jul 19, 2011·3 cites·4 claims
- 2165US7487476B2Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis toolIBM·Filed 2006·Granted Feb 3, 2009·2 cites·4 claims
- 2264US8522187B2Method and data processing system to optimize performance of an electric circuit design, data processing program and computer program productFRICKE NIELS·Filed 2011·Granted Aug 27, 2013·3 cites·14 claims
- 2364US7960836B2Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the sameIBM·Filed 2008·Granted Jun 14, 2011·2 cites·20 claims
- 2463US8010916B2Test yield estimate for semiconductor products created from a libraryIBM·Filed 2008·Granted Aug 30, 2011·2 cites·13 claims
- 2562US8010925B2Method and system for placement of electric circuit components in integrated circuit designIBM·Filed 2008·Granted Aug 30, 2011·2 cites·11 claims
- 2660US8056037B2Method for validating logical function and timing behavior of a digital circuit decisionIBM·Filed 2008·Granted Nov 8, 2011·2 cites·12 claims
- 2759US7961932B2Method and apparatus for manufacturing diamond shaped chipsIBM·Filed 2007·Granted Jun 14, 2011·1 cites·4 claims
- 2859US7206308B2Method of providing a non-blocking routing networkIBM·Filed 2002·Granted Apr 17, 2007·4 cites·22 claims
- 2958US7490310B2Method for creating a layout for an electronic circuitIBM·Filed 2006·Granted Feb 10, 2009·4 cites·6 claims
- 3056US7962881B2Via structure to improve routing of wires within an integrated circuitIBM·Filed 2008·Granted Jun 14, 2011·2 cites·21 claims
- 3155US8513663B2Signal repowering chip for 3-dimensional integrated circuitBUEHLER MARKUS·Filed 2010·Granted Aug 20, 2013·1 cites·5 claims
- 3255US8132129B2Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis toolBICKFORD JEANNE P·Filed 2009·Granted Mar 6, 2012·0 cites·11 claims
- 3353US8418090B2Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis toolBICKFORD JEANNE P·Filed 2012·Granted Apr 9, 2013·0 cites·11 claims
- 3450US9256430B2Instruction scheduling approach to improve processor performanceIBM·Filed 2015·Granted Feb 9, 2016·0 cites·14 claims
- 3549US7496874B2Semiconductor yield estimationINETRNAT BUSINESS MACHINES COR·Filed 2005·Granted Feb 24, 2009·1 cites·9 claims
- 3647US8136066B2Apparatus and computer program product for semiconductor yield estimationBICKFORD JEANNE PAULETTE SPENCE·Filed 2008·Granted Mar 13, 2012·0 cites·21 claims
- 3747US2010257503A1Post-routing coupling fixes for integrated circuitsIBM·Filed 2009·Application pending·0 cites
- 3846US7289659B2Method and apparatus for manufacturing diamond shaped chipsIBM·Filed 2003·Granted Oct 30, 2007·2 cites·23 claims
- 3945US7398485B2Yield optimization in router for systematic defectsIBM·Filed 2006·Granted Jul 8, 2008·0 cites·17 claims
- 4044US2008059933A1Method and System for Designing Fan-out Nets Connecting a Signal Source and Plurality of Active Net Elements in an Integrated CircuitIBM·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →