Inventor · disambiguated record
Juan Guillermo Revilla
Also filed as: REVILLA JUAN · REVILLA JUAN G · REVILLA JUAN GUILLERMO
35 granted patents·1 pending application·1,549 citations·filing 1993–2007
98Inventor score
Top patents by PatentIndex Score
36 records- 0195US6173389B1Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processorBILLIONS OF OPERATIONS PER SEC·Filed 1998·Granted Jan 9, 2001·207 cites·22 claims
- 0293US7313739B2Method and apparatus for testing embedded coresANALOG DEVICES INC·Filed 2002·Granted Dec 25, 2007·60 cites·20 claims
- 0393US6606699B2Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bitBOPS INC·Filed 2001·Granted Aug 12, 2003·67 cites·3 claims
- 0491US7568141B2Method and apparatus for testing embedded coresINTEL CORP·Filed 2007·Granted Jul 28, 2009·19 cites·7 claims
- 0591US6557094B2Methods and apparatus for scalable instruction set architecture with dynamic compact instructionsBOPS INC·Filed 2001·Granted Apr 29, 2003·48 cites·35 claims
- 0689US6446191B1Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communicationBOPS INC·Filed 2000·Granted Sep 3, 2002·48 cites·25 claims
- 0787US6321322B1Methods and apparatus for scalable instruction set architecture with dynamic compact instructionsBOPS INC·Filed 2000·Granted Nov 20, 2001·35 cites·20 claims
- 0887US6216223B1Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processorBILLIONS OF OPERATIONS PER SEC·Filed 1999·Granted Apr 10, 2001·122 cites·29 claims
- 0987US6151668AMethods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communicationBILLIONS OF OPERATIONS PER SEC·Filed 1998·Granted Nov 21, 2000·108 cites·41 claims
- 1086US6467036B1Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processorBOPS INC·Filed 2000·Granted Oct 15, 2002·34 cites·24 claims
- 1184US6851041B2Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processorPTS CORP·Filed 2002·Granted Feb 1, 2005·29 cites·27 claims
- 1283US6460120B1Network processor, memory organization and methodsIBM·Filed 1999·Granted Oct 1, 2002·133 cites·17 claims
- 1382USRE41703EMethods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communicationALTERA CORP·Filed 2004·Granted Sep 14, 2010·24 cites·53 claims
- 1482US6775766B2Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processorPTS CORP·Filed 2001·Granted Aug 10, 2004·29 cites·30 claims
- 1582US6101592AMethods and apparatus for scalable instruction set architecture with dynamic compact instructionsBILLIONS OF OPERATIONS PER SEC·Filed 1998·Granted Aug 8, 2000·71 cites·12 claims
- 1680US6081860AAddress pipelining for data transfersIBM·Filed 1997·Granted Jun 27, 2000·92 cites·15 claims
- 1777US6874078B2Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bitPTS CORP·Filed 2003·Granted Mar 29, 2005·17 cites·25 claims
- 1875US7272705B2Early exception detectionANALOG DEVICES INC·Filed 2005·Granted Sep 18, 2007·6 cites·12 claims
- 1975US7174429B2Method for extending the local memory address space of a processorINTEL CORP·Filed 2001·Granted Feb 6, 2007·21 cites·43 claims
- 2075US6848041B2Methods and apparatus for scalable instruction set architecture with dynamic compact instructionsPTS CORP·Filed 2003·Granted Jan 25, 2005·15 cites·31 claims
- 2174US5925118AMethods and architectures for overlapped read and write operationsIBM·Filed 1996·Granted Jul 20, 1999·69 cites·39 claims
- 2272US6219776B1Merged array controller and processing elementBILLIONS OF OPERATIONS PER SEC·Filed 1998·Granted Apr 17, 2001·47 cites·15 claims
- 2371US5884051ASystem, methods and computer program products for flexibly controlling bus access based on fixed and dynamic prioritiesIBM·Filed 1997·Granted Mar 16, 1999·61 cites·21 claims
- 2467US5862353ASystems and methods for dynamically controlling a busIBM·Filed 1997·Granted Jan 19, 1999·48 cites·50 claims
- 2560US6920515B2Early exception detectionANALOG DEVICES INC·Filed 2001·Granted Jul 19, 2005·6 cites·12 claims
- 2659US5553236AMethod and apparatus for testing a clock stopping/starting function of a low power mode in a data processorMOTOROLA INC·Filed 1995·Granted Sep 3, 1996·22 cites·45 claims
- 2758US7360059B2Variable width alignment engine for aligning instructions based on transition between buffersANALOG DEVICES INC·Filed 2006·Granted Apr 15, 2008·1 cites·18 claims
- 2856US5561614AMethod and apparatus for testing pin isolation for an integrated circuit in a low power mode of operationMOTOROLA INC·Filed 1995·Granted Oct 1, 1996·32 cites·33 claims
- 2955US7082516B1Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanismANALOG DEVICES INC·Filed 2000·Granted Jul 25, 2006·4 cites·12 claims
- 3054US7028129B2Method and apparatus for converting an external memory access into a local memory access in a processor coreINTEL CORP·Filed 2001·Granted Apr 11, 2006·3 cites·30 claims
- 3151US5623636AData processing system and method for providing memory access protection using transparent translation registers and default attribute bitsMOTOROLA INC·Filed 1993·Granted Apr 22, 1997·30 cites·13 claims
- 3247US5689659AMethod and apparatus for bursting operand transfers during dynamic bus sizingMOTOROLA INC·Filed 1995·Granted Nov 18, 1997·23 cites·19 claims
- 3346US5926831AMethods and apparatus for control of speculative memory accessesIBM·Filed 1996·Granted Jul 20, 1999·18 cites·10 claims
- 3445US2005223202A1Branch prediction in a pipelined processorINTEL CORP·Filed 2004·Application pending·0 cites
- 3543US7124285B2Peak power reduction when updating future fileANALOG DEVICES INC·Filed 2001·Granted Oct 17, 2006·0 cites·21 claims
- 3642US6789187B2Processor reset and instruction fetchesINTEL CORP·Filed 2000·Granted Sep 7, 2004·0 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →