P
US7568141B2ExpiredUtilityPatentIndex 90

Method and apparatus for testing embedded cores

Assignee: INTEL CORPPriority: Dec 31, 2002Filed: Dec 21, 2007Granted: Jul 28, 2009
Est. expiryDec 31, 2022(expired)· nominal 20-yr term from priority
Inventors:MENON SANKARAN MBASTO LUIS ADINH TIENTOMAZIN THOMASREVILLA JUAN G
G01R 31/318508G11C 29/48G01R 31/318541G01R 31/318555G11C 2029/3202G01R 31/318513G11C 2029/0401
90
PatentIndex Score
19
Cited by
20
References
7
Claims

Abstract

The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores.

Claims

exact text as granted — not AI-modified
1. Apparatus comprising:
 a scan cell operative to function as a capture storage element in a boundary scan test mode, the scan cell having a data input node, a clock input node, a scan in input node, and an output node; 
 an update storage element having an output node and an input node coupled to the output node of the scan cell; 
 an input multiplexer coupled to the data input node of the scan cell, the input multiplexer operative to select between a functional input and a boundary scan test input; 
 a clock multiplexer coupled to the clock input node of the scan cell, the clock multiplexer operative to select between a boundary scan test clock signal and a system clock signal; and 
 an output multiplexer operative to select between the functional input, a signal from the scan cell output node, and the update storage element output node for output. 
 
   
   
     2. The apparatus of  claim 1 , wherein the input multiplexer is operative to select in response to a data register signal. 
   
   
     3. The apparatus of  claim 1 , wherein the clock multiplexer is operative to select in response to a test mode select signal. 
   
   
     4. The apparatus of  claim 1 , wherein the output multiplexer is operative to select in response to a test mode select signal. 
   
   
     5. The apparatus of  claim 1 , wherein the output multiplexer comprises a three-input multiplexer. 
   
   
     6. The apparatus of  claim 5 , wherein:
 the functional input is received on a first input of the three-input multiplexer; 
 the signal from the scan cell output node is received on a second input of the three-input multiplexer; and 
 the update storage element output node is connected to a third input of the three-input multiplexer. 
 
   
   
     7. The apparatus of  claim 1 , further comprising a line connecting the output node of the scan cell to an input of the output multiplexer.

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