Inventor · disambiguated record
Julien Sebot
Also filed as: SEBOT JULIEN · SEBOT JULIEN FEFE
25 granted patents·11 pending applications·147 citations·filing 2002–2025
95Inventor score
Top patents by PatentIndex Score
36 records- 0194US8782377B2Processor to execute shift right merge instructionsSEBOT JULIEN·Filed 2012·Granted Jul 15, 2014·19 cites·13 claims
- 0294US8745358B2Processor to execute shift right merge instructionsSEBOT JULIEN·Filed 2012·Granted Jun 3, 2014·19 cites·11 claims
- 0389US9189237B2Bitstream buffer manipulation with a SIMD merge instructionINTEL CORP·Filed 2012·Granted Nov 17, 2015·6 cites·16 claims
- 0488US7272622B2Method and apparatus for parallel shift right merge of dataINTEL CORP·Filed 2002·Granted Sep 18, 2007·55 cites·22 claims
- 0586US9189238B2Bitstream buffer manipulation with a SIMD merge instructionINTEL CORP·Filed 2013·Granted Nov 17, 2015·4 cites·7 claims
- 0679US11656676B2System, apparatus and method for dynamic thermal distribution of a system on chipINTEL CORP·Filed 2018·Granted May 23, 2023·2 cites·12 claims
- 0779US9218184B2Processor to execute shift right merge instructionsINTEL CORP·Filed 2013·Granted Dec 22, 2015·2 cites·6 claims
- 0874US9182988B2Bitstream buffer manipulation with a SIMD merge instructionINTEL CORP·Filed 2013·Granted Nov 10, 2015·1 cites·19 claims
- 0974US9170814B2Bitstream buffer manipulation with a SIMD merge instructionINTEL CORP·Filed 2012·Granted Oct 27, 2015·1 cites·15 claims
- 1074US9170815B2Bitstream buffer manipulation with a SIMD merge instructionINTEL CORP·Filed 2013·Granted Oct 27, 2015·1 cites·8 claims
- 1174US7685212B2Fast full search motion estimation with SIMD merge instructionINTEL CORP·Filed 2002·Granted Mar 23, 2010·19 cites·33 claims
- 1273US9182987B2Bitstream buffer manipulation with a SIMD merge instructionINTEL CORP·Filed 2013·Granted Nov 10, 2015·1 cites·14 claims
- 1373US9182985B2Bitstream buffer manipulation with a SIMD merge instructionINTEL CORP·Filed 2012·Granted Nov 10, 2015·1 cites·12 claims
- 1472US2025259906A1Thermal performance in hybrid bonded 3d die stacksINTEL CORP·Filed 2025·Application pending·0 cites
- 1571US9037889B2Apparatus and method for determining the number of execution cores to keep active in a processorANANTHAKRISHNAN AVINASH N·Filed 2012·Granted May 19, 2015·2 cites·20 claims
- 1670US12379769B2System, apparatus and method for dynamic thermal distribution of a system on chipINTEL CORP·Filed 2023·Granted Aug 5, 2025·0 cites·18 claims
- 1770US10732973B2Processor to execute shift right merge instructionsINTEL CORP·Filed 2018·Granted Aug 4, 2020·0 cites·21 claims
- 1868US2025231601A1Thermal management in horizontally or vertically stacked diesINTEL CORP·Filed 2025·Application pending·0 cites
- 1967US12327775B2Thermal performance in hybrid bonded 3D die stacksINTEL CORP·Filed 2021·Granted Jun 10, 2025·0 cites·20 claims
- 2066US7395302B2Method and apparatus for performing horizontal addition and subtractionINTEL CORP·Filed 2003·Granted Jul 1, 2008·11 cites·26 claims
- 2164US12242315B2Thermal management in horizontally or vertically stacked diesINTEL CORP·Filed 2021·Granted Mar 4, 2025·0 cites·30 claims
- 2262US10146541B2Processor to execute shift right merge instructionsINTEL CORP·Filed 2015·Granted Dec 4, 2018·0 cites·12 claims
- 2361US8869294B2Mitigating branch prediction and other timing based side channel attacksSEBOT JULIEN·Filed 2007·Granted Oct 21, 2014·2 cites·12 claims
- 2460US11048318B2Reducing microprocessor power with minimal performance impact by dynamically adapting runtime operating configurations using machine learningINTEL CORP·Filed 2019·Granted Jun 29, 2021·1 cites·18 claims
- 2555US2025112204A1Disaggregated processor architectures using selective transfer technologyINTEL CORP·Filed 2023·Application pending·0 cites
- 2654US12456702B2Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chipletsINTEL CORP·Filed 2021·Granted Oct 28, 2025·0 cites·9 claims
- 2753US2025004781A1Method and apparatus to implement adaptive branch prediction throttlingINTEL CORP·Filed 2023·Application pending·0 cites
- 2853US2024063183A1Modular package architecture for voltage regulator-compute-memory circuits with quasi-monolithic chip layersINTEL CORP·Filed 2022·Application pending·0 cites
- 2952US12469820B2Fine-grained disaggregated server architectureINTEL CORP·Filed 2021·Granted Nov 11, 2025·0 cites·20 claims
- 3052US11537375B2Digitally coordinated dynamically adaptable clock and voltage supply apparatus and methodINTEL CORP·Filed 2019·Granted Dec 27, 2022·0 cites·17 claims
- 3150US2022415853A1Heat insulating interconnect features in a component of a composite ic device structureINTEL CORP·Filed 2021·Application pending·0 cites
- 3250US2022406751A1Quasi-monolithic hierarchical integration architectureINTEL CORP·Filed 2021·Application pending·0 cites
- 3349US2023317729A1Vertical bit data paths for integrated circuitsINTEL CORP·Filed 2022·Application pending·0 cites
- 3448US2023284457A1Interconnects with spintronic logic devicesINTEL CORP·Filed 2022·Application pending·0 cites
- 3548US2023100228A1Physical and electrical protocol translation chipletsINTEL CORP·Filed 2021·Application pending·0 cites
- 3648US2015241954A1Apparatus and Method for Determining the Number of Execution Units to Keep Active in a ProcessorANANTHAKRISHNAN AVINASH N·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →