US2015241954A1PendingUtilityA1

Apparatus and Method for Determining the Number of Execution Units to Keep Active in a Processor

48
Individually held — no corporate assignee on recordPriority: Sep 28, 2012Filed: Apr 27, 2015Published: Aug 27, 2015
Est. expirySep 28, 2032(~6.2 yrs left)· nominal 20-yr term from priority
Inventors:Avinash N. AnanthakrishnanJulien SebotJay D. SchwartzStephen H. GuntherEric C. Samson
G06F 1/3293G06F 1/3206G06F 1/324G06F 1/3287Y02D10/00
48
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Claims

Abstract

A processor is described that includes a plurality of execution units in a processor core. The processor also may include power management circuitry to determine a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units for a same active performance state. A method may include determining with power management circuitry of a processor a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units in a processor core of the processor for a same active performance state.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A processor comprising:
 a plurality of execution units in a processor core; and   power management circuitry to determine a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units for a same active performance state.   
     
     
         2 . The processor of  claim 1 , wherein the power management circuitry is to determine the configuration with the lowest power cost from a change in power consumption for a unit change in frequency for each of the plurality of configurations. 
     
     
         3 . The processor of  claim 2 , wherein the change in power consumption includes a leakage power consumption. 
     
     
         4 . The processor of  claim 1 , wherein the power management circuitry is to switch the processor core to the configuration with the lowest power cost. 
     
     
         5 . The processor of  claim 1 , wherein the power management circuitry is to detect a change in a performance state of the processor core to the same active performance state. 
     
     
         6 . The processor of  claim 1 , wherein the power management circuitry is to accept one or more dynamic input variables. 
     
     
         7 . The processor of  claim 6 , wherein the one or more dynamic input variables include any of:
 supply voltage;   temperature; and   activity level of an execution unit.   
     
     
         8 . The processor of  claim 1 , wherein the power management circuitry is to accept one or more static input variables. 
     
     
         9 . The processor of  claim 8 , wherein the one or more static input variables include any of:
 a switching capacitance term to determine dynamic power consumption;   a reference current term to determine leakage power consumption; and   a set of manufacturing related parameters to determine how a reference leakage and switching capacitance scale with temperature and voltage.   
     
     
         10 . A method comprising:
 determining with power management circuitry of a processor a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units in a processor core of the processor for a same active performance state.   
     
     
         11 . The method of  claim 10 , wherein the determining comprises determining the configuration with the lowest power cost from a change in power consumption for a unit change in frequency for each of the plurality of configurations. 
     
     
         12 . The method of  claim 11 , wherein the change in power consumption includes a leakage power consumption. 
     
     
         13 . The method of  claim 10 , further comprising switching the processor core to the configuration with the lowest power cost. 
     
     
         14 . The method of  claim 10 , further comprising detecting a change in a performance state of the processor core to the same active performance state. 
     
     
         15 . The method of  claim 10 , wherein the determining includes accepting one or more dynamic input variables. 
     
     
         16 . The method of  claim 15 , wherein the one or more dynamic input variables include any of:
 supply voltage;   temperature; and   activity level of an execution unit.   
     
     
         17 . The method of  claim 10 , wherein the determining includes accepting one or more static input variables. 
     
     
         18 . The method of  claim 17 , wherein the one or more static input variables include any of:
 a switching capacitance term to determine dynamic power consumption;   a reference current term to determine leakage power consumption; and   a set of manufacturing related parameters to determine how a reference leakage and switching capacitance scale with temperature and voltage.   
     
     
         19 . A non-transitory machine readable storage medium having stored program code that when processed by a machine causes a method to be performed, the method comprising:
 determining with power management circuitry of a processor a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units in a processor core of the processor for a same active performance state.   
     
     
         20 . The non-transitory machine readable storage medium of  claim 19 , the method comprising:
 wherein the determining comprises determining the configuration with the lowest power cost from a change in power consumption for a unit change in frequency for each of the plurality of configurations.   
     
     
         21 . The non-transitory machine readable storage medium of  claim 20 , the method comprising:
 wherein the change in power consumption includes a leakage power consumption.   
     
     
         22 . The non-transitory machine readable storage medium of  claim 19 , the method further comprising switching the processor core to the configuration with the lowest power cost. 
     
     
         23 . The non-transitory machine readable storage medium of  claim 19 , the method further comprising detecting a change in a performance state of the processor core to the same active performance state. 
     
     
         24 . The non-transitory machine readable storage medium of  claim 19 , the method comprising:
 wherein the determining includes accepting one or more dynamic input variables.   
     
     
         25 . The non-transitory machine readable storage medium of  claim 19 , the method comprising:
 wherein the determining includes accepting one or more static input variables.

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