Inventor · disambiguated record
Jy-Hwang Lin
Also filed as: LIN JY-HWANG
11 granted patents·4 pending applications·141 citations·filing 1998–2017
90Inventor score
Top patents by PatentIndex Score
15 records- 0189US7091079B2Method of forming devices having three different operation voltagesUNITED MICROELECTRONICS CORP·Filed 2004·Granted Aug 15, 2006·56 cites·29 claims
- 0263US9978795B1Semiconductor structureUNITED MICROELECTRONICS CORP·Filed 2017·Granted May 22, 2018·1 cites·20 claims
- 0363US7256092B2Method for fabricating integrated circuits having both high voltage and low voltage devicesUNITED MICROELECTRONICS CORP·Filed 2004·Granted Aug 14, 2007·10 cites·12 claims
- 0462US6900097B2Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltageUNITED MICROELECTRONICS CORP·Filed 2003·Granted May 31, 2005·15 cites·9 claims
- 0557US6133143AMethod of manufacturing interconnectUNITED SEMICONDUCTOR CORP·Filed 1999·Granted Oct 17, 2000·22 cites·11 claims
- 0649US7005339B2Method of integrating high voltage metal oxide semiconductor devices and submicron metal oxide semiconductor devicesUNITED MICROELECTRONICS CORP·Filed 2003·Granted Feb 28, 2006·4 cites·25 claims
- 0744US6150916AArchitecture of poly fusesUNITED MICROELECTRONICS CORP·Filed 1998·Granted Nov 21, 2000·13 cites·5 claims
- 0842US6083825AMethod of forming unlanded via holeUNITED SEMICONDUCTOR CORP·Filed 1999·Granted Jul 4, 2000·10 cites·13 claims
- 0941US6462390B1Multi-film capping layer for a salicide processUNITED MICROELECTRONICS CORP·Filed 2000·Granted Oct 8, 2002·2 cites·16 claims
- 1038US6165895AFabrication method of an interconnectUNITED SEMICONDUCTOR CORP·Filed 1999·Granted Dec 26, 2000·8 cites·13 claims
- 1137US2010240181A1Method for Forming Single-Level Electrically Erasable and Programmable Read Only Memory Operated in Environment with High/Low-VoltageUNITED MICROELECTRONICS CORP·Filed 2010·Application pending·0 cites
- 1236US2007063349A1Interconnect structure and method of manufacturing the sameKAO TSUI-LIEN·Filed 2005·Application pending·0 cites
- 1335US2001009248A1Metal etching processFiled 2001·Application pending·0 cites
- 1435US2001009249A1Metal etching processFiled 2001·Application pending·0 cites
- 1528USRE44156EMethod for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltageCHEN RONG-CHING·Filed 2006·Granted Apr 16, 2013·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →