Inventor · disambiguated record
Kang Chen
Also filed as: CHEN KANG · CHEN KANG-I
120 granted patents·2 pending applications·1,811 citations·filing 2002–2022
99Inventor score
Files withSTATS CHIPPAC LTD50LIN YAOJIAN40STATS CHIPPAC PTE LTD24JCET SEMICONDUCTOR SHAOXING CO LTD2CHEN KANG1
Top patents by PatentIndex Score
122 records- 0198US10297518B2Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale packageSTATS CHIPPAC PTE LTD·Filed 2016·Granted May 21, 2019·47 cites·23 claims
- 0298US9679863B2Semiconductor device and method of forming interconnect substrate for FO-WLCSPLIN YAOJIAN·Filed 2011·Granted Jun 13, 2017·59 cites·5 claims
- 0398US9385006B2Semiconductor device and method of forming an embedded SOP fan-out packageLIN YAOJIAN·Filed 2012·Granted Jul 5, 2016·71 cites·32 claims
- 0498US9082806B2Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSPLIN YAOJIAN·Filed 2011·Granted Jul 14, 2015·72 cites·20 claims
- 0598US9064936B2Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSPSTATS CHIPPAC LTD·Filed 2013·Granted Jun 23, 2015·58 cites·12 claims
- 0698US8994185B2Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSPSTATS CHIPPAC LTD·Filed 2013·Granted Mar 31, 2015·44 cites·35 claims
- 0798US8810024B2Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect unitsLIN YAOJIAN·Filed 2012·Granted Aug 19, 2014·62 cites·32 claims
- 0898US8796846B2Semiconductor device with a vertical interconnect structure for 3-D FO-WLCSPLIN YAOJIAN·Filed 2009·Granted Aug 5, 2014·108 cites·32 claims
- 0998US8193604B2Semiconductor package with semiconductor core structure and method of forming the sameLIN YAOJIAN·Filed 2010·Granted Jun 5, 2012·152 cites·24 claims
- 1098US7858441B2Semiconductor package with semiconductor core structure and method of forming sameSTATS CHIPPAC LTD·Filed 2008·Granted Dec 28, 2010·75 cites·23 claims
- 1198US7642128B1Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSPSTATS CHIPPAC LTD·Filed 2008·Granted Jan 5, 2010·144 cites·20 claims
- 1297US10304817B2Semiconductor device and method of forming build-up interconnect structures over a temporary substrateSTATS CHIPPAC PTE LTD·Filed 2017·Granted May 28, 2019·17 cites·22 claims
- 1397US9842798B2Semiconductor device and method of forming a PoP device with embedded vertical interconnect unitsSTATS CHIPPAC LTD·Filed 2013·Granted Dec 12, 2017·31 cites·6 claims
- 1497US9548240B2Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor packageSTATS CHIPPAC LTD·Filed 2015·Granted Jan 17, 2017·20 cites·25 claims
- 1597US8592992B2Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSPLIN YAOJIAN·Filed 2011·Granted Nov 26, 2013·34 cites·30 claims
- 1697US8445323B2Semiconductor package with semiconductor core structure and method of forming sameLIN YAOJIAN·Filed 2012·Granted May 21, 2013·37 cites·28 claims
- 1797US7772081B2Semiconductor device and method of forming high-frequency circuit structure and method thereofSTATS CHIPPAC LTD·Filed 2008·Granted Aug 10, 2010·67 cites·18 claims
- 1897US7691747B2Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structuresSTATS CHIPPAC LTD·Filed 2007·Granted Apr 6, 2010·62 cites·19 claims
- 1996US11024561B2Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect unitsSTATS CHIPPAC PTE LTD·Filed 2020·Granted Jun 1, 2021·3 cites·25 claims
- 2096US10049964B2Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect unitsSTATS CHIPPAC LTD·Filed 2013·Granted Aug 14, 2018·21 cites·22 claims
- 2196US9768155B2Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSPSTATS CHIPPAC LTD·Filed 2015·Granted Sep 19, 2017·14 cites·19 claims
- 2296US9527723B2Semiconductor device and method of forming microelectromechanical systems (MEMS) packageSTATS CHIPPAC LTD·Filed 2015·Granted Dec 27, 2016·25 cites·12 claims
- 2396US8343809B2Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor dieSTATS CHIPPAC LTD·Filed 2010·Granted Jan 1, 2013·23 cites·27 claims
- 2495US10217702B2Semiconductor device and method of forming an embedded SoP fan-out packageSTATS CHIPPAC PTE LTD·Filed 2016·Granted Feb 26, 2019·13 cites·23 claims
- 2595US9818734B2Semiconductor device and method of forming build-up interconnect structures over a temporary substrateSTATS CHIPPAC LTD·Filed 2015·Granted Nov 14, 2017·12 cites·25 claims
- 2695US9368563B2Semiconductor device including integrated passive device formed over semiconductor die with conductive bridge and fan-out redistribution layerSTATS CHIPPAC LTD·Filed 2013·Granted Jun 14, 2016·19 cites·24 claims
- 2794US9685350B2Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLBSTATS CHIPPAC LTD·Filed 2014·Granted Jun 20, 2017·16 cites·6 claims
- 2894US9385102B2Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale packageSTATS CHIPPAC LTD·Filed 2012·Granted Jul 5, 2016·17 cites·27 claims
- 2994US9318404B2Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP packageSTATS CHIPPAC LTD·Filed 2013·Granted Apr 19, 2016·19 cites·21 claims
- 3094US8907476B2Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulationLIN YAOJIAN·Filed 2012·Granted Dec 9, 2014·12 cites·24 claims
- 3194US8786100B2Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor dieSTATS CHIPPAC LTD·Filed 2012·Granted Jul 22, 2014·14 cites·25 claims
- 3294US8456002B2Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress reliefLIN YAOJIAN·Filed 2011·Granted Jun 4, 2013·13 cites·25 claims
- 3394US8168470B2Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compoundLIN YAOJIAN·Filed 2008·Granted May 1, 2012·28 cites·27 claims
- 3494US7790503B2Semiconductor device and method of forming integrated passive device moduleSTATS CHIPPAC LTD·Filed 2007·Granted Sep 7, 2010·32 cites·22 claims
- 3593US10475779B2Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSPSTATS CHIPPAC PTE LTD·Filed 2017·Granted Nov 12, 2019·7 cites·25 claims
- 3693US9837303B2Semiconductor method and device of forming a fan-out device with PWB vertical interconnect unitsSTATS CHIPPAC LTD·Filed 2013·Granted Dec 5, 2017·16 cites·23 claims
- 3793US8445990B2Semiconductor device and method of forming an inductor within interconnect layer vertically separated from semiconductor dieLIN YAOJIAN·Filed 2010·Granted May 21, 2013·18 cites·24 claims
- 3893US8409926B2Semiconductor device and method of forming insulating layer around semiconductor dieLIN YAOJIAN·Filed 2010·Granted Apr 2, 2013·12 cites·24 claims
- 3992US10189702B2Semiconductor device and method of forming microelectromechanical systems (MEMS) packageSTATS CHIPPAC PTE LTD·Filed 2016·Granted Jan 29, 2019·4 cites·23 claims
- 4092US9293401B2Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)STATS CHIPPAC LTD·Filed 2013·Granted Mar 22, 2016·11 cites·22 claims
- 4192US8648470B2Semiconductor device and method of forming FO-WLCSP with multiple encapsulantsLIN YAOJIAN·Filed 2011·Granted Feb 11, 2014·12 cites·24 claims
- 4292US8624353B2Semiconductor device and method of forming integrated passive device over semiconductor die with conductive bridge and fan-out redistribution layerLIN YAOJIAN·Filed 2011·Granted Jan 7, 2014·13 cites·30 claims
- 4391US9607958B2Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formationSTATS CHIPPAC LTD·Filed 2014·Granted Mar 28, 2017·10 cites·19 claims
- 4491US9449943B2Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper patternSTATS CHIPPAC LTD·Filed 2014·Granted Sep 20, 2016·10 cites·23 claims
- 4590US10192796B2Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSPSTATS CHIPPAC LTD·Filed 2013·Granted Jan 29, 2019·7 cites·23 claims
- 4690US9875973B2Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layersSTATS CHIPPAC LTD·Filed 2013·Granted Jan 23, 2018·11 cites·17 claims
- 4790US9865525B2Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect unitsSTATS CHIPPAC LTD·Filed 2014·Granted Jan 9, 2018·9 cites·25 claims
- 4890US9847324B2Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSPSTATS CHIPPAC LTD·Filed 2015·Granted Dec 19, 2017·7 cites·20 claims
- 4989US9082780B2Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layerLIN YAOJIAN·Filed 2012·Granted Jul 14, 2015·10 cites·25 claims
- 5089US8492203B2Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layersLIN YAOJIAN·Filed 2011·Granted Jul 23, 2013·10 cites·13 claims
Showing the top 50 of 122 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →