Inventor · disambiguated record
Kaushik De
Also filed as: DE KAUSHIK
17 granted patents·1 pending application·270 citations·filing 1995–2021
93Inventor score
Top patents by PatentIndex Score
18 records- 0193US11467851B1Machine learning (ML)-based static verification for derived hardware-design elementsSYNOPSYS INC·Filed 2020·Granted Oct 11, 2022·3 cites·20 claims
- 0288US10878153B1Apparatuses and methods for accurate and efficient clock domain and reset domain verification with register transfer level memory inferenceSYNOPSYS INC·Filed 2019·Granted Dec 29, 2020·9 cites·11 claims
- 0388US5663967ADefect isolation using scan-path testing and electron beam probing in multi-level high density asicsLSI LOGIC CORP·Filed 1995·Granted Sep 2, 1997·99 cites·4 claims
- 0485US11550979B2Implementing and verifying safety measures in a system design based on safety specification generated from safety requirementsSYNOPSYS INC·Filed 2021·Granted Jan 10, 2023·2 cites·20 claims
- 0579US6135647ASystem and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL codeLSI LOGIC CORP·Filed 1997·Granted Oct 24, 2000·83 cites·15 claims
- 0678US9529948B2Minimizing crossover paths for functional verification of a circuit descriptionSYNOPSYS INC·Filed 2014·Granted Dec 27, 2016·5 cites·30 claims
- 0778US7797123B2Method and apparatus for extracting assume properties from a constrained random test-benchSYNOPSYS INC·Filed 2008·Granted Sep 14, 2010·10 cites·18 claims
- 0871US9032339B2Ranking verification results for root cause analysisSYNOPSYS INC·Filed 2013·Granted May 12, 2015·3 cites·30 claims
- 0963US9792394B2Accurate glitch detectionSYNOPSYS INC·Filed 2016·Granted Oct 17, 2017·1 cites·20 claims
- 1061US5638380AProtecting proprietary asic design information using boundary scan on selective inputs and outputsLSI LOGIC CORP·Filed 1996·Granted Jun 10, 1997·24 cites·22 claims
- 1159US5903578ATest shells for protecting proprietary information in asic coresLSI LOGIC CORP·Filed 1996·Granted May 11, 1999·23 cites·8 claims
- 1254US11947885B1Low-power static signoff verification from within an implementation toolSYNOPSYS INC·Filed 2021·Granted Apr 2, 2024·0 cites·20 claims
- 1354US8479128B2Technique for honoring multi-cycle path semantics in RTL simulationDE KAUSHIK·Filed 2011·Granted Jul 2, 2013·1 cites·21 claims
- 1450US11222154B2State table complexity reduction in a hierarchical verification flowSYNOPSYS INC·Filed 2020·Granted Jan 11, 2022·0 cites·20 claims
- 1545US9886753B2Verification of circuit structures including sub-structure variantsSYNOPSYS INC·Filed 2014·Granted Feb 6, 2018·0 cites·19 claims
- 1644US10706192B1Voltage reconciliation in multi-level power managed systemsSYNOPSYS INC·Filed 2018·Granted Jul 7, 2020·0 cites·14 claims
- 1741US2016180012A1Low Power Verification Method for a Circuit Description and System for Automating a Minimization of a Circuit DescriptionSYNOPSYS INC·Filed 2014·Application pending·0 cites
- 1833US6212655B1IDDQ test solution for large asicsLSI LOGIC CORP·Filed 1997·Granted Apr 3, 2001·7 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →