Inventor · disambiguated record
Kathryn Guarini
Also filed as: GUARINI KATHRYN · GUARINI KATHRYN W · GUARINI KATHRYN WILDER
36 granted patents·7 pending applications·2,097 citations·filing 2000–2015
98Inventor score
Top patents by PatentIndex Score
43 records- 0199US7723207B2Three dimensional integrated circuit and method of designIBM·Filed 2007·Granted May 25, 2010·277 cites·13 claims
- 0299US7312487B2Three dimensional integrated circuitIBM·Filed 2004·Granted Dec 25, 2007·335 cites·11 claims
- 0399US6821826B1Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafersIBM·Filed 2003·Granted Nov 23, 2004·391 cites·19 claims
- 0498US7045851B2Nonvolatile memory device using semiconductor nanocrystals and method of forming sameIBM·Filed 2003·Granted May 16, 2006·169 cites·27 claims
- 0597US7329923B2High-performance CMOS devices on hybrid crystal oriented substratesIBM·Filed 2003·Granted Feb 12, 2008·138 cites·5 claims
- 0697US6830962B1Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processesIBM·Filed 2003·Granted Dec 14, 2004·134 cites·17 claims
- 0795US7244958B2Integration of strained Ge into advanced CMOS technologyIBM·Filed 2004·Granted Jul 17, 2007·82 cites·9 claims
- 0895US6506660B2Semiconductor with nanoscale featuresIBM·Filed 2001·Granted Jan 14, 2003·101 cites·18 claims
- 0993US6645861B2Self-aligned silicide process for silicon sidewall source and drain contactsIBM·Filed 2001·Granted Nov 11, 2003·71 cites·35 claims
- 1092US7453123B2Self-aligned planar double-gate transistor structureIBM·Filed 2007·Granted Nov 18, 2008·15 cites·1 claims
- 1192US6911375B2Method of fabricating silicon devices on sapphire with wafer bonding at low temperatureIBM·Filed 2003·Granted Jun 28, 2005·64 cites·19 claims
- 1292US6555880B2Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed therebyIBM·Filed 2001·Granted Apr 29, 2003·54 cites·9 claims
- 1391US6358813B1Method for increasing the capacitance of a semiconductor capacitorsIBM·Filed 2000·Granted Mar 19, 2002·56 cites·30 claims
- 1489US6444578B1Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devicesIBM·Filed 2001·Granted Sep 3, 2002·50 cites·50 claims
- 1588US7387925B2Integration of strained Ge into advanced CMOS technologyIBM·Filed 2007·Granted Jun 17, 2008·12 cites·1 claims
- 1686US7205185B2Self-aligned planar double-gate process by self-aligned oxidationIBM·Filed 2003·Granted Apr 17, 2007·26 cites·18 claims
- 1785US8987138B2Nonvolatile memory device using semiconductor nanocrystals and method of forming sameBLACK CHARLES T·Filed 2011·Granted Mar 24, 2015·4 cites·15 claims
- 1885US8247292B2Nonvolative memory device using semiconductor nanocrystals and method of forming sameBLACK CHARLES T·Filed 2011·Granted Aug 21, 2012·4 cites·5 claims
- 1981US8273665B2Nonvolatile memory device using semiconductor nanocrystals and method forming sameBLACK CHARLES T·Filed 2009·Granted Sep 25, 2012·4 cites·7 claims
- 2081US7985686B2Method of forming a nonvolatile memory device using semiconductor nanoparticlesIBM·Filed 2006·Granted Jul 26, 2011·4 cites·12 claims
- 2178US6716708B2Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed therebyIBM·Filed 2002·Granted Apr 6, 2004·20 cites·31 claims
- 2275US7790538B2Integration of strained Ge into advanced CMOS technologyIBM·Filed 2008·Granted Sep 7, 2010·4 cites·8 claims
- 2374US8358011B1Interconnect structures with engineered dielectrics with nanocolumnar porosityIBM·Filed 2007·Granted Jan 22, 2013·6 cites·1 claims
- 2474US7713807B2High-performance CMOS SOI devices on hybrid crystal-oriented substratesIBM·Filed 2007·Granted May 11, 2010·5 cites·17 claims
- 2574US7268432B2Interconnect structures with engineered dielectrics with nanocolumnar porosityIBM·Filed 2003·Granted Sep 11, 2007·17 cites·7 claims
- 2669US7342301B2Connection device with actuating element for changing a conductive state of a viaIBM·Filed 2006·Granted Mar 11, 2008·3 cites·16 claims
- 2768US8901741B2Interconnect structures with engineered dielectrics with nanocolumnar porosityCOLBURN MATTHEW E·Filed 2012·Granted Dec 2, 2014·2 cites·11 claims
- 2866US6803266B2Process for passivating the semiconductor-dielectric interface of a MOS device and MOS device formed therebyIBM·Filed 2003·Granted Oct 12, 2004·9 cites·20 claims
- 2966US6603181B2MOS device having a passivated semiconductor-dielectric interfaceIBM·Filed 2001·Granted Aug 5, 2003·9 cites·7 claims
- 3065US7713837B2Low temperature fusion bonding with high surface energy using a wet chemical treatmentIBM·Filed 2008·Granted May 11, 2010·2 cites·14 claims
- 3165US7187059B2Compressive SiGe <110> growth and structure of MOSFET devicesIBM·Filed 2004·Granted Mar 6, 2007·11 cites·9 claims
- 3258US7566631B2Low temperature fusion bonding with high surface energy using a wet chemical treatmentIBM·Filed 2006·Granted Jul 28, 2009·1 cites·1 claims
- 3357US7138683B2Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processesIBM·Filed 2004·Granted Nov 21, 2006·6 cites·8 claims
- 3457US7074707B2Method of fabricating a connection deviceIBM·Filed 2003·Granted Jul 11, 2006·6 cites·14 claims
- 3556US2015200277A1Nonvolatile memory device using semiconductor nanocrystals and method of forming sameIBM·Filed 2015·Application pending·0 cites
- 3655US7498640B2Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed therebyIBM·Filed 2003·Granted Mar 3, 2009·5 cites·31 claims
- 3754US7960790B2Self-aligned planar double-gate transistor structureIBM·Filed 2008·Granted Jun 14, 2011·0 cites·18 claims
- 3854US2008042140A1Three dimensional integrated circuit and method of designIBM·Filed 2007·Application pending·0 cites
- 3944US2008165521A1Three-dimensional architecture for self-checking and self-repairing integrated circuitsBERNSTEIN KERRY·Filed 2007·Application pending·0 cites
- 4044US2005067620A1Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafersIBM·Filed 2004·Application pending·0 cites
- 4142US2004124092A1Inorganic nanoporous membranes and methods to form sameFiled 2002·Application pending·0 cites
- 4239US2004126993A1Low temperature fusion bonding with high surface energy using a wet chemical treatmentFiled 2002·Application pending·0 cites
- 4338US2004142578A1Thin film nanostructuresFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →