Low temperature fusion bonding with high surface energy using a wet chemical treatment

Abstract

Described is a wet chemical surface treatment involving NH 4 OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO 2 ) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m 2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of 2500 mJ/m 2 have also be achieved herein.

Having thus described our invention in detail, what we claim is new and desire to secure by the Letters Patent is:  
     
         1 . A method of bonding two wafers having a bonded surface area comprising the steps of: 
 providing a first wafer having a substantially out-gassed oxide layer formed on a surface thereof, said oxide layer being formed at a temperature T 1 ;    providing a second wafer having a surface;    treating the substantially out-gassed oxide layer of the first wafer and the surface of the second wafer with a solution containing NH 4 OH;    contacting the treated surfaces with each other; and    annealing the two wafers at a temperature T 2  which is less than or equal to T 1  thereby forming a bonded wafer pair which has a surface energy of about 2000 mJ/m 2  or greater and a bonded interface that has a dislocation density of less than 106 cm −2  and a void/bubble density of less than about 1% of the bonded surface area.    
     
     
         2 . The method of  claim 1  wherein said out-gassed oxide layer is formed by oxidation followed by annealing.  
     
     
         3 . The method of  claim 1  wherein said out-gassed oxide layer is formed by deposition followed by annealing.  
     
     
         4 . The method of  claim 1  wherein T 1  is equal to or less than 400° C.  
     
     
         5 . The method of  claim 1  wherein T 1  is from about room temperature to about 300° C.  
     
     
         6 . The method of  claim 1  wherein said substantially out-gassed oxide layer contains little or no surface hydroxyl groups and/or physisorbed water.  
     
     
         7 . The method of  claim 1  wherein said substantially out-gassed oxide layer and said surface are polished prior to said treating to provide surfaces having a root mean square surface roughness of less than about 0.5 nm.  
     
     
         8 . The method of  claim 1  wherein said treating is performed at about room temperature.  
     
     
         9 . The method of  claim 1  wherein a drying step is performed between said treating and said annealing.  
     
     
         10 . The method of  claim 1  wherein a rinsing step and a drying step are performed between said treating and said annealing.  
     
     
         11 . The method of  claim 1  wherein T 2  is equal to or less than 400° C.  
     
     
         12 . The method of  claim 1  wherein T 2  is from about room temperature to about 300° C.  
     
     
         13 . The method of  claim 1  wherein said annealing is performed in an inert gas ambient.  
     
     
         14 . The method of  claim 1  wherein an external force is applied during said contacting and said annealing.  
     
     
         15 . A bonded wafer pair having a bonded surface area comprising: 
 an oxide layer located between a bottom wafer and a top wafer, said oxide layer having an interface with the top wafer that has a dislocation density of less than 106 cm −2  and a void/bubble density of less than about 1% of the bonded surface area and wherein the top wafer has a surface energy of about 2000 mJ/m 2  or greater.    
     
     
         16 . The bonded wafer pair of  claim 15  wherein said top wafer and said bottom wafer are the same or different and are selected from a semiconducting substrate or an insulating substrate.  
     
     
         17 . The bonded wafer pair of  claim 15  wherein said top and bottom wafers are both comprised of a semiconducting substrate.  
     
     
         18 . The bonded wafer pair of  claim 17  wherein said semiconducting substrate is a Si-containing material.  
     
     
         19 . The bonded wafer pair of  claim 15  wherein said bottom wafer is sapphire and said top wafer is a Si-containing material.  
     
     
         20 . An integrated circuit comprising at least the bonded wafer pair of  claim 15.