Inventor · disambiguated record
Leathen Shi
Also filed as: SHI III LEATHEN · SHI LEATHEN
53 granted patents·9 pending applications·2,203 citations·filing 1990–2018
99Inventor score
Top patents by PatentIndex Score
62 records- 0199US8927968B2Accurate control of distance between suspended semiconductor nanowires and substrate surfaceIBM·Filed 2013·Granted Jan 6, 2015·87 cites·14 claims
- 0299US6224690B1Flip-Chip interconnections using lead-free soldersIBM·Filed 1996·Granted May 1, 2001·191 cites·12 claims
- 0399US5371654AThree dimensional high performance interconnection packageIBM·Filed 1992·Granted Dec 6, 1994·503 cites·25 claims
- 0498US5531022AMethod of forming a three dimensional high performance interconnection packageIBM·Filed 1994·Granted Jul 2, 1996·328 cites·15 claims
- 0597US6830962B1Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processesIBM·Filed 2003·Granted Dec 14, 2004·134 cites·17 claims
- 0697US6660598B2Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel regionIBM·Filed 2002·Granted Dec 9, 2003·137 cites·10 claims
- 0796US7087965B2Strained silicon CMOS on hybrid crystal orientationsIBM·Filed 2004·Granted Aug 8, 2006·97 cites·13 claims
- 0896US5062896ASolder/polymer composite paste and methodIBM·Filed 1990·Granted Nov 5, 1991·96 cites·16 claims
- 0995US8030145B2Back-gated fully depleted SOI transistorIBM·Filed 2010·Granted Oct 4, 2011·23 cites·21 claims
- 1094US6841831B2Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate processIBM·Filed 2003·Granted Jan 11, 2005·74 cites·10 claims
- 1192US6911375B2Method of fabricating silicon devices on sapphire with wafer bonding at low temperatureIBM·Filed 2003·Granted Jun 28, 2005·64 cites·19 claims
- 1291US9355936B2Flattened substrate surface for substrate bondingGLOBALFOUNDRIES INC·Filed 2014·Granted May 31, 2016·16 cites·20 claims
- 1390US6399406B2Encapsulated MEMS band-pass filter for integrated circuits and method of fabrication thereofIBM·Filed 2001·Granted Jun 4, 2002·44 cites·12 claims
- 1490US5424634ANon-destructive flex testing method and meansIBM·Filed 1994·Granted Jun 13, 1995·120 cites·4 claims
- 1589US7235812B2Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniquesIBM·Filed 2004·Granted Jun 26, 2007·41 cites·12 claims
- 1686US9536853B2Semiconductor device including built-in crack-arresting film structureIBM·Filed 2014·Granted Jan 3, 2017·3 cites·6 claims
- 1786US6686630B2Damascene double-gate MOSFET structure and its fabrication methodIBM·Filed 2001·Granted Feb 3, 2004·44 cites·4 claims
- 1884US7767546B1Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layerIBM·Filed 2009·Granted Aug 3, 2010·12 cites·22 claims
- 1983US6835633B2SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layerIBM·Filed 2002·Granted Dec 28, 2004·24 cites·7 claims
- 2082US7445977B2Method of creating defect free high Ge content (> 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniquesIBM·Filed 2007·Granted Nov 4, 2008·7 cites·1 claims
- 2182US7402466B2Strained silicon CMOS on hybrid crystal orientationsIBM·Filed 2006·Granted Jul 22, 2008·8 cites·1 claims
- 2282US6262464B1Encapsulated MEMS brand-pass filter for integrated circuitsIBM·Filed 2000·Granted Jul 17, 2001·23 cites·27 claims
- 2380US7488630B2Method for preparing 2-dimensional semiconductor devices for integration in a third dimensionIBM·Filed 2007·Granted Feb 10, 2009·9 cites·13 claims
- 2480US7485518B2Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)IBM·Filed 2007·Granted Feb 3, 2009·6 cites·1 claims
- 2579US7704815B2Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniquesIBM·Filed 2008·Granted Apr 27, 2010·5 cites·24 claims
- 2678US8778737B2Flattened substrate surface for substrate bondingCOONEY III EDWARD C·Filed 2011·Granted Jul 15, 2014·4 cites·22 claims
- 2778US8492838B2Isolation structures for SOI devices with ultrathin SOI and ultrathin boxDENNARD ROBERT H·Filed 2009·Granted Jul 23, 2013·6 cites·14 claims
- 2876US7528056B2Low-cost strained SOI substrate for high-performance CMOS technologyIBM·Filed 2007·Granted May 5, 2009·5 cites·16 claims
- 2975US7217949B2Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)IBM·Filed 2004·Granted May 15, 2007·11 cites·10 claims
- 3072US9865469B2Epitaxial lift-off process with guided etchingIBM·Filed 2017·Granted Jan 9, 2018·1 cites·18 claims
- 3172US8877606B2Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolationDENNARD ROBERT H·Filed 2012·Granted Nov 4, 2014·2 cites·6 claims
- 3269US8927405B2Accurate control of distance between suspended semiconductor nanowires and substrate surfaceIBM·Filed 2012·Granted Jan 6, 2015·2 cites·12 claims
- 3369US8408262B2Adaptive chuck for planar bonding between substratesGUO DECHAO·Filed 2009·Granted Apr 2, 2013·2 cites·20 claims
- 3468US8637381B2High-k dielectric and silicon nitride box regionLEOBANDUNG EFFENDI·Filed 2011·Granted Jan 28, 2014·2 cites·12 claims
- 3567US7897480B2Preparation of high quality strained-semiconductor directly-on-insulator substratesIBM·Filed 2007·Granted Mar 1, 2011·4 cites·7 claims
- 3665US10615139B2Semiconductor device including built-in crack-arresting film structureIBM·Filed 2018·Granted Apr 7, 2020·0 cites·4 claims
- 3765US7713837B2Low temperature fusion bonding with high surface energy using a wet chemical treatmentIBM·Filed 2008·Granted May 11, 2010·2 cites·14 claims
- 3864US8586426B2Method of forming isolation structures for SOI devices with ultrathin SOI and ultrathin boxDENNARD ROBERT H·Filed 2012·Granted Nov 19, 2013·1 cites·20 claims
- 3963US10211178B2Semiconductor device including built-in crack-arresting film structureIBM·Filed 2017·Granted Feb 19, 2019·0 cites·5 claims
- 4063US5721602AMechanical packaging and thermal management of flat mirror arraysIBM·Filed 1995·Granted Feb 24, 1998·25 cites·20 claims
- 4162US10020279B2Semiconductor device including built-in crack-arresting film structureIBM·Filed 2016·Granted Jul 10, 2018·0 cites·6 claims
- 4258US8017499B2Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)IBM·Filed 2008·Granted Sep 13, 2011·0 cites·15 claims
- 4358US7566631B2Low temperature fusion bonding with high surface energy using a wet chemical treatmentIBM·Filed 2006·Granted Jul 28, 2009·1 cites·1 claims
- 4457US7507989B2Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)IBM·Filed 2007·Granted Mar 24, 2009·0 cites·1 claims
- 4557US7138683B2Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processesIBM·Filed 2004·Granted Nov 21, 2006·6 cites·8 claims
- 4656US5764314AMechanical packaging and thermal management of flat mirror arraysIBM·Filed 1996·Granted Jun 9, 1998·20 cites·10 claims
- 4755US2010176482A1Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolationIBM·Filed 2009·Application pending·0 cites
- 4854US7691688B2Strained silicon CMOS on hybrid crystal orientationsIBM·Filed 2008·Granted Apr 6, 2010·0 cites·18 claims
- 4951US7521735B2Multiple layer and crystal plane orientation semiconductor substrateIBM·Filed 2008·Granted Apr 21, 2009·0 cites·11 claims
- 5051US7166521B2SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layerIBM·Filed 2004·Granted Jan 23, 2007·2 cites·17 claims
Showing the top 50 of 62 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →