Inventor · disambiguated record
Karem A. Sakallah
Also filed as: SAKALLAH KAREM · SAKALLAH KAREM A
7 granted patents·1 pending application·94 citations·filing 1998–2013
85Inventor score
Technology areasG06F
Files withCADENCE DESIGN SYSTEMS INC4ANDRAUS ZAHER1SAKALLAH KAREM A1UNIV MICHIGAN1WESTERN MICHIGAN UNIVERSITY RES FOUNDATION1
Top patents by PatentIndex Score
8 records- 0178US8954909B2Automated scalable verification for hardware designs at the register transfer levelUNIV MICHIGAN·Filed 2013·Granted Feb 10, 2015·6 cites·19 claims
- 0275US8601414B2Automated scalable verification for hardware designs at the register transfer levelANDRAUS ZAHER·Filed 2010·Granted Dec 3, 2013·8 cites·20 claims
- 0364US6442739B1System and method for timing abstraction of digital logic circuitsCADENCE DESIGN SYSTEMS INC·Filed 1998·Granted Aug 27, 2002·42 cites·33 claims
- 0458US6877143B1System and method for timing abstraction of digital logic circuitsCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Apr 5, 2005·6 cites·21 claims
- 0558US6457159B1Functional timing analysis for characterization of virtual component blocksCADENCE DESIGN SYSTEMS INC·Filed 1999·Granted Sep 24, 2002·30 cites·12 claims
- 0651US9389983B2Verification of complex systems that can be described by a finite state transition systemSAKALLAH KAREM A·Filed 2013·Granted Jul 12, 2016·1 cites·11 claims
- 0748US7346872B2Functional timing analysis for characterization of virtual component blocksCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Mar 18, 2008·1 cites·19 claims
- 0839US2013283101A1Trace-Driven Verification of Multithreaded Programs Using SMT-Based AnalysisWESTERN MICHIGAN UNIVERSITY RES FOUNDATION·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →