Inventor · disambiguated record
Keith Dennison
Also filed as: DENNISON KEITH
12 granted patents·114 citations·filing 2005–2014
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
12 records- 0192US8261228B1Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracyGOPALAKRISHNAN PRAKASH·Filed 2008·Granted Sep 4, 2012·42 cites·14 claims
- 0287US8769456B1Methods, systems, and articles for implementing extraction and electrical analysis-driven module creationKRISHNAN PRAKASH·Filed 2011·Granted Jul 1, 2014·13 cites·37 claims
- 0385US9047424B1System and method for analog verification IP authoring and storageCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jun 2, 2015·8 cites·23 claims
- 0485US8584072B1Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracyGOPALAKRISHNAN PRAKASH·Filed 2012·Granted Nov 12, 2013·9 cites·17 claims
- 0583US9589085B1Systems and methods for viewing analog simulation check violations in an electronic design automation frameworkCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 7, 2017·8 cites·20 claims
- 0683US8694933B2Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awarenessGOPALAKRISHNAN PRAKASH·Filed 2010·Granted Apr 8, 2014·5 cites·54 claims
- 0781US8612921B1Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracyGOPALAKRISHNAN PRAKASH·Filed 2012·Granted Dec 17, 2013·6 cites·8 claims
- 0879US9223925B2Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awarenessCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 29, 2015·3 cites·27 claims
- 0979US8694950B2Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awarenessMCSHERRY MICHAEL·Filed 2010·Granted Apr 8, 2014·4 cites·35 claims
- 1076US9501598B1System and method for assertion publication and re-useCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Nov 22, 2016·4 cites·17 claims
- 1174US7277804B2Method and system for performing effective resistance calculation for a network of resistorsCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Oct 2, 2007·10 cites·56 claims
- 1269US9286420B1Methods, systems, and articles for implementing extraction and electrical analysis-driven module creationCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 15, 2016·2 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →