Inventor · disambiguated record
Kedar Janardan Dhori
Also filed as: DHORI KEDAR JANARDAN
25 granted patents·12 pending applications·23 citations·filing 2008–2025
92Inventor score
Files withST MICROELECTRONICS INT NV33ST MICROELECTRONICS SRL2DHORI KEDAR JANARDAN1STMICROELECTRONICS FRANCE1
Top patents by PatentIndex Score
37 records- 0189US11984151B2Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted May 14, 2024·3 cites·32 claims
- 0288US12087356B2Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Sep 10, 2024·2 cites·33 claims
- 0382US9865333B2Temperature compensated read assist circuit for a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2016·Granted Jan 9, 2018·7 cites·22 claims
- 0481US9685209B1Circuit for generating a sense amplifier enable signal with variable timingST MICROELECTRONICS INT NV·Filed 2016·Granted Jun 20, 2017·6 cites·29 claims
- 0576US2025308574A1Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 0673US9940997B2Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operationST MICROELECTRONICS INT NV·Filed 2017·Granted Apr 10, 2018·3 cites·31 claims
- 0768US2025078883A1Bit-cell architecture based in-memory computeST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 0867US2025069652A1Circuitry for adjusting retention voltage of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 0967US2025174269A1Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 1066US2024395319A1Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1166US2025069678A1Built-in self test circuit for segmented static random access memory (sram) array input/outputST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1265US12183424B2Bit-cell architecture based in-memory computeST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 31, 2024·0 cites·33 claims
- 1365US11726543B2Computing system power management device, system and methodST MICROELECTRONICS SRL·Filed 2020·Granted Aug 15, 2023·0 cites·19 claims
- 1464US12292780B2Computing system power management device, system and methodST MICROELECTRONICS SRL·Filed 2023·Granted May 6, 2025·0 cites·14 claims
- 1563US12437825B2At-speed transition fault testing for a multi-port and multi-clock memoryST MICROELECTRONICS INT NV·Filed 2023·Granted Oct 7, 2025·0 cites·40 claims
- 1662US12482518B2Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read currentST MICROELECTRONICS INT NV·Filed 2023·Granted Nov 25, 2025·0 cites·12 claims
- 1762US12469545B2Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2023·Granted Nov 11, 2025·0 cites·42 claims
- 1862US12170120B2Built-in self test circuit for segmented static random access memory (SRAM) array input/outputST MICROELECTRONICS INT NV·Filed 2023·Granted Dec 17, 2024·0 cites·38 claims
- 1961US12328858B2Silicon-on-insulator semiconductor device with a static random access memory circuitSTMICROELECTRONICS FRANCE·Filed 2023·Granted Jun 10, 2025·0 cites·22 claims
- 2061US12165698B2Circuitry for adjusting retention voltage of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2021·Granted Dec 10, 2024·0 cites·22 claims
- 2160US12237007B2Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Feb 25, 2025·0 cites·39 claims
- 2259US12354644B2Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Jul 8, 2025·0 cites·30 claims
- 2356US12353341B2Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selectionST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 8, 2025·0 cites·19 claims
- 2454US12406705B2In-memory computation circuit using static random access memory (SRAM) array segmentationST MICROELECTRONICS INT NV·Filed 2023·Granted Sep 2, 2025·0 cites·24 claims
- 2548US12361982B2Memory architecture supporting both conventional memory access mode and digital in-memory computation processing modeST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 15, 2025·0 cites·19 claims
- 2648US11758707B2SRAM cell layout including arrangement of multiple active regions and multiple gate regionsST MICROELECTRONICS INT NV·Filed 2020·Granted Sep 12, 2023·0 cites·20 claims
- 2747US9208040B2Repair control logic for safe memories having redundant elementsST MICROELECTRONICS INT NV·Filed 2014·Granted Dec 8, 2015·0 cites·20 claims
- 2847US2024363187A1Area saving high coverage fast diagnosis memory scan designST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 2946US2024177769A1Bit line accumulation readout scheme for an analog in-memory computation processing circuitST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 3044US12400707B2Device and method for reading data from memory cellsST MICROELECTRONICS INT NV·Filed 2021·Granted Aug 26, 2025·0 cites·18 claims
- 3144US10224097B2Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operationST MICROELECTRONICS INT NV·Filed 2018·Granted Mar 5, 2019·0 cites·10 claims
- 3244US2023386565A1In-memory computation circuit using static random access memory (sram) array segmentation and local compute tile read based on weighted currentST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 3344US2024112728A1Analog in-memory computation processing circuit using segmented memory architectureST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 3444US2023386566A1Bit line voltage clamping read circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 3542US12176025B2Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 24, 2024·0 cites·51 claims
- 3641US8154936B2Single-ended bit line based storage systemDHORI KEDAR JANARDAN·Filed 2008·Granted Apr 10, 2012·2 cites·12 claims
- 3736US2021327501A1Lower power memory write operationST MICROELECTRONICS INT NV·Filed 2021·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Kedar Janardan Dhori files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →