Inventor · disambiguated record
Kenneth S. Mcelvain
Also filed as: MCELVAIN KENNETH · MCELVAIN KENNETH S
106 granted patents·4 pending applications·2,393 citations·filing 1998–2016
99Inventor score
Top patents by PatentIndex Score
110 records- 0198US7366997B1Methods and apparatuses for thermal analysis based circuit designSYNPLICITY INC·Filed 2005·Granted Apr 29, 2008·288 cites·33 claims
- 0296US7827510B1Enhanced hardware debugging with embedded FPGAS in a hardware description languageSYNOPSYS INC·Filed 2007·Granted Nov 2, 2010·88 cites·45 claims
- 0395US8701068B2Interconnection device in a multi-layer shielding meshSYNOPSYS INC·Filed 2013·Granted Apr 15, 2014·13 cites·21 claims
- 0495US7739624B2Methods and apparatuses to generate a shielding mesh for integrated circuit devicesSYNOPSYS INC·Filed 2005·Granted Jun 15, 2010·27 cites·5 claims
- 0595US7240303B1Hardware/software co-debugging in a hardware description languageSYNPLICITY INC·Filed 2003·Granted Jul 3, 2007·132 cites·57 claims
- 0694US8881086B2Integrated circuit devices and methods and apparatuses for designing integrated circuit devicesMCELVAIN KENNETH S·Filed 2012·Granted Nov 4, 2014·15 cites·20 claims
- 0794US7093204B2Method and apparatus for automated synthesis of multi-channel circuitsSYNPLICITY INC·Filed 2003·Granted Aug 15, 2006·75 cites·42 claims
- 0893US7594211B1Methods and apparatuses for reset conditioning in integrated circuitsSYNOPSYS INC·Filed 2006·Granted Sep 22, 2009·33 cites·30 claims
- 0993US7200822B1Circuits with modular redundancy and methods and apparatuses for their automated synthesisSYNPLICITY INC·Filed 2004·Granted Apr 3, 2007·59 cites·135 claims
- 1092US7627844B2Methods and apparatuses for transient analyses of circuitsSYNOPSYS INC·Filed 2007·Granted Dec 1, 2009·26 cites·27 claims
- 1192US6711729B1Methods and apparatuses for designing integrated circuits using automatic reallocation techniquesSYNPLICITY INC·Filed 2000·Granted Mar 23, 2004·109 cites·80 claims
- 1292US6668364B2Methods and apparatuses for designing integrated circuitsSYNPLICITY INC·Filed 2002·Granted Dec 23, 2003·63 cites·48 claims
- 1390US8386979B2Method and apparatus to design an interconnection device in a multi-layer shielding meshSYNOPSYS INC·Filed 2009·Granted Feb 26, 2013·11 cites·20 claims
- 1490US8176452B2Method and apparatus for circuit partitioning and trace assignment in circuit designPANDEY AWARTIKA·Filed 2010·Granted May 8, 2012·12 cites·21 claims
- 1590US7941779B2Methods and apparatuses for thermal analysis based circuit designSYNOPSYS INC·Filed 2008·Granted May 10, 2011·17 cites·19 claims
- 1690US6904576B2Method and system for debugging using replicated logicSYNPLICITY INC·Filed 2002·Granted Jun 7, 2005·35 cites·27 claims
- 1790US6438735B1Methods and apparatuses for designing integrated circuitsSYNPLICITY INC·Filed 1999·Granted Aug 20, 2002·118 cites·104 claims
- 1888US8458639B2Circuit partitioning and trace assignment in circuit designPANDEY AWARTIKA·Filed 2012·Granted Jun 4, 2013·9 cites·21 claims
- 1988US7943436B2Integrated circuit devices and methods and apparatuses for designing integrated circuit devicesSYNOPSYS INC·Filed 2003·Granted May 17, 2011·37 cites·92 claims
- 2088US7278120B2Methods and apparatuses for transient analyses of circuitsSYNPLICITY INC·Filed 2004·Granted Oct 2, 2007·45 cites·51 claims
- 2188US7237214B1Method and apparatus for circuit partitioning and trace assignment in circuit designSYNPLICITY INC·Filed 2004·Granted Jun 26, 2007·37 cites·27 claims
- 2288US6449762B1Maintaining correspondence between text and schematic representations of circuit elements in circuit synthesisSYNPLICITY INC·Filed 1999·Granted Sep 10, 2002·135 cites·31 claims
- 2387US7665046B2Method and system for debugging using replicated logic and trigger logicSYNOPSYS INC·Filed 2007·Granted Feb 16, 2010·11 cites·3 claims
- 2486US8286118B2Integrated circuit devices and methods and apparatuses for designing integrated circuit devicesMCELVAIN KENNETH S·Filed 2011·Granted Oct 9, 2012·6 cites·72 claims
- 2586US7178118B2Method and apparatus for automated circuit designSYNPLICITY INC·Filed 2004·Granted Feb 13, 2007·41 cites·63 claims
- 2686US7007254B1Method and apparatus for the design and analysis of digital circuits with time division multiplexingSYNPLICITY INC·Filed 2003·Granted Feb 28, 2006·34 cites·36 claims
- 2786US6687882B1Methods and apparatuses for non-equivalence checking of circuits with subspaceSYNPLICITY INC·Filed 2002·Granted Feb 3, 2004·44 cites·33 claims
- 2884US10268797B2Architectural physical synthesisSYNOPSYS INC·Filed 2013·Granted Apr 23, 2019·7 cites·20 claims
- 2984US8307315B2Methods and apparatuses for circuit design and optimizationADYA SAURABH·Filed 2009·Granted Nov 6, 2012·15 cites·30 claims
- 3084US8171441B2Integrated circuit devices and methods and apparatuses for designing integrated circuit devicesMCELVAIN KENNETH S·Filed 2009·Granted May 1, 2012·7 cites·18 claims
- 3184US8074197B2Shielding mesh design for an integrated circuit deviceMCELVAIN KENNETH S·Filed 2009·Granted Dec 6, 2011·7 cites·15 claims
- 3284US7844930B2Method and apparatus for circuit partitioning and trace assignment in circuit designSYNOPSYS INC·Filed 2007·Granted Nov 30, 2010·9 cites·20 claims
- 3384US7454732B2Methods and apparatuses for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICsSYNOPSYS INC·Filed 2005·Granted Nov 18, 2008·10 cites·36 claims
- 3484US6519754B1Methods and apparatuses for designing integrated circuitsSYNPLICITY INC·Filed 1999·Granted Feb 11, 2003·81 cites·73 claims
- 3583US8141024B2Temporally-assisted resource sharing in electronic systemsMARKOV IGOR L·Filed 2008·Granted Mar 20, 2012·12 cites·64 claims
- 3683US7251800B2Method and apparatus for automated circuit designSYNPLICITY INC·Filed 2004·Granted Jul 31, 2007·45 cites·76 claims
- 3783US6735743B1Method and apparatus for invalid state detectionSYNPLICITY INC·Filed 2001·Granted May 11, 2004·30 cites·84 claims
- 3883US6643829B1Reducing clock skew in clock gating circuitsSYNPLICITY INC·Filed 2001·Granted Nov 4, 2003·35 cites·15 claims
- 3982US9038013B2Circuit partitioning and trace assignment in circuit designSYNOPSYS INC·Filed 2013·Granted May 19, 2015·4 cites·21 claims
- 4082US8729922B2Licensing programmable hardware sub-designs using a host-identifierMCELVAIN KENNETH S·Filed 2011·Granted May 20, 2014·5 cites·26 claims
- 4182US8572535B2Thermal analysis based circuit designRAHMAT KHALID·Filed 2011·Granted Oct 29, 2013·5 cites·21 claims
- 4282US8161437B2Method and apparatus for automated synthesis of multi-channel circuitsOKTEM LEVENT·Filed 2009·Granted Apr 17, 2012·8 cites·21 claims
- 4382US7500205B2Skew reduction for generated clocksSYNOPSYS INC·Filed 2006·Granted Mar 3, 2009·12 cites·51 claims
- 4482US6973632B1Method and apparatus to estimate delay for logic circuit optimizationSYNPLICITY INC·Filed 2002·Granted Dec 6, 2005·39 cites·72 claims
- 4581US9208281B2Optimizing designs of integrated circuitsSYNOPSYS INC·Filed 2014·Granted Dec 8, 2015·4 cites·20 claims
- 4681US8122412B2Shelding mesh design for an integrated circuit deviceMCELVAIN KENNETH S·Filed 2009·Granted Feb 21, 2012·5 cites·14 claims
- 4781US7434187B2Method and apparatus to estimate delay for logic circuit optimizationSYNOPSYS INC·Filed 2005·Granted Oct 7, 2008·13 cites·28 claims
- 4881US7350173B1Method and apparatus for placement and routing cells on integrated circuit chipsSYNPLICITY INC·Filed 2003·Granted Mar 25, 2008·35 cites·18 claims
- 4980US7908574B2Techniques for use with automated circuit design and simulationsSYNOPSYS INC·Filed 2008·Granted Mar 15, 2011·11 cites·28 claims
- 5080US7010769B2Methods and apparatuses for designing integrated circuitsSYNPLICITY INC·Filed 2002·Granted Mar 7, 2006·21 cites·99 claims
Showing the top 50 of 110 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →