Inventor · disambiguated record
Ken Wadland
Also filed as: WADLAND KEN
21 granted patents·247 citations·filing 2001–2011
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0187US7793249B1Method and system for adaptive bundling of connections in user-guided autoroutingCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Sep 7, 2010·23 cites·23 claims
- 0287US7536665B1User-guided autoroutingCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted May 19, 2009·26 cites·11 claims
- 0387US7464358B1Method for resolving overloads in autorouting physical interconnectionsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Dec 9, 2008·14 cites·8 claims
- 0486US7761836B1Circuit autorouter with object oriented constraintsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jul 20, 2010·20 cites·27 claims
- 0584US7620922B1Method and system for optimized circuit autoroutingCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Nov 17, 2009·14 cites·34 claims
- 0683US8510703B1Method and mechanism for implementing PCB routingWADLAND KEN·Filed 2005·Granted Aug 13, 2013·18 cites·42 claims
- 0783US7574686B1Method and system for implementing deterministic multi-processingCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Aug 11, 2009·14 cites·40 claims
- 0881US8086987B1Method for resolving overloads in autorouting physical interconnectionsWADLAND KEN·Filed 2011·Granted Dec 27, 2011·5 cites·8 claims
- 0980US8191032B1Budgeting global constraints on local constraints in an autorouterWADLAND KEN·Filed 2009·Granted May 29, 2012·10 cites·20 claims
- 1079US8250514B1Localized routing directionWADLAND KEN·Filed 2006·Granted Aug 21, 2012·11 cites·37 claims
- 1178US8789060B1Deterministic, parallel execution with overlapping regionsWADLAND KEN·Filed 2007·Granted Jul 22, 2014·10 cites·18 claims
- 1277US6516447B2Topological global routing for automated IC package interconnectCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Feb 4, 2003·24 cites·17 claims
- 1376US8549459B1Systems for automatic circuit routing with object oriented constraintsWADLAND KEN·Filed 2010·Granted Oct 1, 2013·5 cites·15 claims
- 1476US8082533B1Method for resolving overloads in autorouting physical interconnectionsWADLAND KEN·Filed 2011·Granted Dec 20, 2011·3 cites·3 claims
- 1576US7017137B2Topological global routing for automated IC package interconnectCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Mar 21, 2006·22 cites·41 claims
- 1675US8151239B1Method for resolving overloads in autorouting physical interconnectionsWADLAND KEN·Filed 2008·Granted Apr 3, 2012·5 cites·19 claims
- 1771US8479138B1Global constraint optimizationLAWSON RANDALL SCOTT·Filed 2009·Granted Jul 2, 2013·6 cites·37 claims
- 1871US7562330B1Budgeting global constraints on local constraints in an autorouterCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jul 14, 2009·5 cites·18 claims
- 1970US7937681B2Method and mechanism for implementing automated PCB routingCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted May 3, 2011·7 cites·20 claims
- 2065US8146042B1Method and system for optimized circuit autoroutingWADLAND KEN·Filed 2009·Granted Mar 27, 2012·3 cites·27 claims
- 2149US7594215B2Method and system for optimized automated IC package pin routingCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Sep 22, 2009·2 cites·46 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →