Inventor · disambiguated record
Khalid Mohiuddin Sirajuddin
Also filed as: SIRAJUDDIN KHALID · SIRAJUDDIN KHALID M · SIRAJUDDIN KHALID MOHIUDDIN
5 granted patents·6 pending applications·14 citations·filing 2008–2015
69Inventor score
Top patents by PatentIndex Score
11 records- 0182US8158522B2Method of forming a deep trench in a substrateSIRAJUDDIN KHALID M·Filed 2010·Granted Apr 17, 2012·10 cites·16 claims
- 0279US10903055B2Edge ring for bevel polymer reductionAPPLIED MATERIALS INC·Filed 2015·Granted Jan 26, 2021·4 cites·9 claims
- 0346US2009272717A1Method and apparatus of a substrate etching system and processAPPLIED MATERIALS INC·Filed 2009·Application pending·0 cites
- 0441US2014335679A1Methods for etching a substrateAPPLIED MATERIALS INC·Filed 2013·Application pending·0 cites
- 0539US9039908B2Post etch reactive plasma milling to smooth through substrate via sidewalls and other deeply etched featuresFARR JON·Filed 2008·Granted May 26, 2015·0 cites·16 claims
- 0638US2014179108A1Wafer Edge Protection and Efficiency Using Inert Gas and RingAPPLIED MATERIALS INC·Filed 2013·Application pending·0 cites
- 0737US9023227B2Increased deposition efficiency and higher chamber conductance with source power increase in an inductively coupled plasma (ICP) chamberDINEV JIVKO·Filed 2012·Granted May 5, 2015·0 cites·20 claims
- 0837US2014199833A1Methods for performing a via reveal etching process for forming through-silicon vias in a substrateAPPLIED MATERIALS INC·Filed 2014·Application pending·0 cites
- 0934US8987140B2Methods for etching through-silicon vias with tunable profile anglesBAJAJ PUNEET·Filed 2012·Granted Mar 24, 2015·0 cites·17 claims
- 1034US2013288474A1Methods for fabricating dual damascene interconnect structuresMISHRA ROHIT·Filed 2012·Application pending·0 cites
- 1134US2011217832A1Method of filling a deep trench in a substrateRAORANE DIGVIJAY·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →