Inventor · disambiguated record
Kinya Ichikawa
Also filed as: ICHIKAWA KINYA
21 granted patents·6 pending applications·814 citations·filing 1996–2020
96Inventor score
Top patents by PatentIndex Score
27 records- 0199US9349703B2Method for making high density substrate interconnect using inkjet printingINTEL CORP·Filed 2013·Granted May 24, 2016·111 cites·10 claims
- 0298US9741664B2High density substrate interconnect formed through inkjet printingINTEL CORP·Filed 2016·Granted Aug 22, 2017·32 cites·20 claims
- 0398US7345361B2Stackable integrated circuit packagingINTEL CORP·Filed 2003·Granted Mar 18, 2008·307 cites·13 claims
- 0495US6020561APrinted circuit substrate with solder formed on pad-on-via and pad-off-via contacts thereofINTEL CORP·Filed 1996·Granted Feb 1, 2000·138 cites·4 claims
- 0589US7495330B2Substrate connector for integrated circuit devicesINTEL CORP·Filed 2005·Granted Feb 24, 2009·18 cites·22 claims
- 0686US6632704B2Molded flip chip packageINTEL CORP·Filed 2000·Granted Oct 14, 2003·31 cites·2 claims
- 0785US7132311B2Encapsulation of a stack of semiconductor diceINTEL CORP·Filed 2002·Granted Nov 7, 2006·41 cites·27 claims
- 0883US9502368B2Picture frame stiffeners for microelectronic packagesINTEL CORP·Filed 2014·Granted Nov 22, 2016·5 cites·11 claims
- 0982US8110920B2In-package microelectronic apparatus, and methods of using sameDATTAGURU SRIRAM·Filed 2009·Granted Feb 7, 2012·11 cites·2 claims
- 1077US6838313B2Molded flip chip packageINTEL CORP·Filed 2003·Granted Jan 4, 2005·16 cites·17 claims
- 1174US7097462B2Patch substrate for external connectionINTEL CORP·Filed 2004·Granted Aug 29, 2006·17 cites·23 claims
- 1273US5660321AMethod for controlling solder bump height and volume for substrates containing both pad-on and pad-off via contactsINTEL CORP·Filed 1996·Granted Aug 26, 1997·31 cites·20 claims
- 1368US9685388B2Picture frame stiffeners for microelectronic packagesINTEL CORP·Filed 2016·Granted Jun 20, 2017·1 cites·11 claims
- 1468US7132739B2Encapsulated stack of dice and support thereforINTEL CORP·Filed 2004·Granted Nov 7, 2006·14 cites·18 claims
- 1560US6342791B1Diode defect detecting deviceNAS TOA CO LTD·Filed 2000·Granted Jan 29, 2002·15 cites·9 claims
- 1652US9263329B2Methods of connecting a first electronic package to a second electronic packageINTEL CORP·Filed 2014·Granted Feb 16, 2016·0 cites·20 claims
- 1752US7005729B2Device packaging using tape automated bonding (TAB) strip bonded to strip carrier frameINTEL CORP·Filed 2002·Granted Feb 28, 2006·4 cites·13 claims
- 1847US11362246B2Method of manufacturing display device with lateral wiringNICHIA CORP·Filed 2020·Granted Jun 14, 2022·0 cites·13 claims
- 1947US2006191134A1Patch substrate for external connectionICHIKAWA KINYA·Filed 2006·Application pending·0 cites
- 2046US11410975B2Display device and method of manufacturing display deviceNICHIA CORP·Filed 2020·Granted Aug 9, 2022·0 cites·24 claims
- 2142US2007231475A1Conductor structure on dielectric materialSHIMOTO TADANORI·Filed 2006·Application pending·0 cites
- 2241US6785148B1Easy mount socketINTEL CORP·Filed 1998·Granted Aug 31, 2004·8 cites·14 claims
- 2340US5811883ADesign for flip chip joint pad/LGA padINTEL CORP·Filed 1996·Granted Sep 22, 1998·14 cites·26 claims
- 2440US2002114144A1Molded flip chip packageFiled 2002·Application pending·0 cites
- 2540US2005217787A1Tape automated bonding with strip carrier frame assemblyMURAKAMI YUKIHIRO·Filed 2005·Application pending·0 cites
- 2637US2012112336A1Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic packageGUZEK JOHN S·Filed 2010·Application pending·0 cites
- 2735US2002110956A1Chip lead framesFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →