Inventor · disambiguated record
Korbin S. Van Dyke
Also filed as: VAN DYKE KORBIN · VAN DYKE KORBIN S
76 granted patents·1 pending application·6,620 citations·filing 1985–2012
99Inventor score
Top patents by PatentIndex Score
77 records- 0199US7047394B1Computer for execution of RISC and CISC instruction setsATI INT SRL·Filed 2000·Granted May 16, 2006·318 cites·72 claims
- 0298US7661107B1Method and apparatus for dynamic allocation of processing resourcesADVANCED MICRO DEVICES INC·Filed 2000·Granted Feb 9, 2010·195 cites·13 claims
- 0398US6499123B1Method and apparatus for debugging an integrated circuitADVANCED MICRO DEVICES INC·Filed 2000·Granted Dec 24, 2002·221 cites·5 claims
- 0498US6397379B1Recording in a program execution profile references to a memory-mapped active deviceATI INT SRL·Filed 1999·Granted May 28, 2002·343 cites·47 claims
- 0598US5226126AProcessor having plurality of functional units for orderly retiring outstanding operations based upon its associated tagsNEXGEN MICROSYSTEMS·Filed 1990·Granted Jul 6, 1993·449 cites·8 claims
- 0697US8356144B2Vector processor systemHESSEL RICHARD·Filed 2009·Granted Jan 15, 2013·411 cites·18 claims
- 0796US8788792B2Apparatus for executing programs for a first computer architecture on a computer of a second architectureYATES JR JOHN S·Filed 2012·Granted Jul 22, 2014·53 cites·20 claims
- 0896US8127121B2Apparatus for executing programs for a first computer architechture on a computer of a second architechtureYATES JR JOHN S·Filed 2007·Granted Feb 28, 2012·98 cites·18 claims
- 0996US6549959B1Detecting modification to computer memory by a DMA deviceATI INT SRL·Filed 1999·Granted Apr 15, 2003·286 cites·60 claims
- 1096US6321314B1Method and apparatus for restricting memory accessATI INT SRL·Filed 1999·Granted Nov 20, 2001·265 cites·25 claims
- 1196US5226130AMethod and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistencyNEXGEN MICROSYSTEMS·Filed 1990·Granted Jul 6, 1993·300 cites·4 claims
- 1295US7065633B1System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPUATI INT SRL·Filed 2000·Granted Jun 20, 2006·152 cites·44 claims
- 1395US6934832B1Exception mechanism for a computerATI INT SRL·Filed 2000·Granted Aug 23, 2005·152 cites·71 claims
- 1494US8121828B2Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditionsYATES JR JOHN S·Filed 2004·Granted Feb 21, 2012·86 cites·28 claims
- 1594US6941545B1Profiling of computer programs executing in virtual memory systemsATI INT SRL·Filed 1999·Granted Sep 6, 2005·171 cites·81 claims
- 1694US5454117AConfigurable branch prediction for a processor performing speculative executionNEXGEN INC·Filed 1993·Granted Sep 26, 1995·171 cites·3 claims
- 1793US6954923B1Recording classification of instructions executed by a computerATI INT SRL·Filed 1999·Granted Oct 11, 2005·211 cites·35 claims
- 1893US5442757AComputer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interruptsNEXGEN INC·Filed 1993·Granted Aug 15, 1995·147 cites·56 claims
- 1993US5163140ATwo-level branch prediction cacheNEXGEN MICROSYSTEMS·Filed 1992·Granted Nov 10, 1992·145 cites·3 claims
- 2092US7013456B1Profiling execution of computer programsATI INT SRL·Filed 1999·Granted Mar 14, 2006·188 cites·45 claims
- 2191US7941647B2Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop terminationATI TECHNOLOGIES ULC·Filed 2007·Granted May 10, 2011·26 cites·54 claims
- 2290US7228404B1Managing instruction side-effectsATI INT SRL·Filed 2000·Granted Jun 5, 2007·66 cites·52 claims
- 2390US6763452B1Modifying program execution based on profilingATI INT SRL·Filed 1999·Granted Jul 13, 2004·148 cites·36 claims
- 2490US5781753ASemi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructionsADVANCED MICRO DEVICES INC·Filed 1995·Granted Jul 14, 1998·134 cites·61 claims
- 2590US5230068ACache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequenceNEXGEN MICROSYSTEMS·Filed 1990·Granted Jul 20, 1993·139 cites·5 claims
- 2689US8065504B2Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processorYATES JR JOHN S·Filed 2004·Granted Nov 22, 2011·56 cites·27 claims
- 2789US5768575ASemi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructionsADVANCED MICRO DEVICES INC·Filed 1995·Granted Jun 16, 1998·166 cites·19 claims
- 2887US7254806B1Detecting reordered side-effectsATI INT SRL·Filed 1999·Granted Aug 7, 2007·120 cites·64 claims
- 2986US7543119B2Vector processorHESSEL RICHARD EDWARD·Filed 2006·Granted Jun 2, 2009·18 cites·15 claims
- 3086US5515518ATwo-level branch prediction cacheNEXGEN INC·Filed 1994·Granted May 7, 1996·80 cites·31 claims
- 3184US6671798B1Configurable branch prediction for a processor performing speculative executionADVANCED MICRO DEVICES INC·Filed 2001·Granted Dec 30, 2003·28 cites·24 claims
- 3283US5623614ABranch prediction cache with multiple entries for returns having multiple callersADVANCED MICRO DEVICES INC·Filed 1993·Granted Apr 22, 1997·93 cites·25 claims
- 3382US7069421B1Side tables annotating an instruction streamATI TECHNOLOGIES SRL·Filed 1999·Granted Jun 27, 2006·74 cites·77 claims
- 3481US6449671B1Method and apparatus for busing data elementsATI INT SRL·Filed 1999·Granted Sep 10, 2002·97 cites·24 claims
- 3580US6826748B1Profiling program execution into registers of a computerATI INT SRL·Filed 1999·Granted Nov 30, 2004·77 cites·27 claims
- 3680US6282639B1Configurable branch prediction for a processor performing speculative executionADVANCED MICRO DEVICES INC·Filed 2000·Granted Aug 28, 2001·20 cites·5 claims
- 3777US6789181B1Safety net paradigm for managing two computer execution modesATI INT SRL·Filed 1999·Granted Sep 7, 2004·56 cites·48 claims
- 3876US6775414B1Variable-length code decoderATI INT SRL·Filed 1999·Granted Aug 10, 2004·37 cites·41 claims
- 3976US6212629B1Method and apparatus for executing string instructionsADVANCED MICRO DEVICES INC·Filed 1998·Granted Apr 3, 2001·56 cites·22 claims
- 4076US4626825ALogarithmic conversion apparatusVLSI TECHNOLOGY INC·Filed 1985·Granted Dec 2, 1986·56 cites·1 claims
- 4175US5327547ATwo-level branch prediction cacheNEXGEN MICROSYSTEMS·Filed 1992·Granted Jul 5, 1994·46 cites·12 claims
- 4274US8074055B1Altering data storage conventions of a processor when execution flows from first architecture code to second architecture codeYATES JR JOHN S·Filed 1999·Granted Dec 6, 2011·73 cites·47 claims
- 4374US5802339APipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unitADVANCED MICRO DEVICES INC·Filed 1997·Granted Sep 1, 1998·56 cites·28 claims
- 4473US5881265AComputer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interruptsADVANCED MICRO DEVICES INC·Filed 1995·Granted Mar 9, 1999·47 cites·17 claims
- 4572US5093778AIntegrated single structure branch prediction cacheNEXGEN MICROSYSTEMS·Filed 1990·Granted Mar 3, 1992·61 cites·6 claims
- 4671US8412916B2Computing system having CPU and bridge operating using CPU frequencySFARTI ADRIAN·Filed 2010·Granted Apr 2, 2013·2 cites·9 claims
- 4771US8086055B2Variable-length code decoderFOGG CHAD E·Filed 2009·Granted Dec 27, 2011·2 cites·17 claims
- 4870US8381223B2Method and apparatus for dynamic allocation of processing resourcesVAN DYKE KORBIN·Filed 2011·Granted Feb 19, 2013·3 cites·18 claims
- 4967US5511175AMethod an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistencyNEXGEN INC·Filed 1994·Granted Apr 23, 1996·40 cites·11 claims
- 5066US6654872B1Variable length instruction alignment device and methodATI INT SRL·Filed 2000·Granted Nov 25, 2003·11 cites·13 claims
Showing the top 50 of 77 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →